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| 型号： | SL28SRC02BZI |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 7/14页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK PCIE GEN3/2 DIF 20TSSOP |
| 标准包装： | 75 |
| 类型： | * |
| PLL： | 是 |
| 输入： | 时钟，晶体 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 100MHz |
| 除法器/乘法器： | 无/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
SL28SRC02
............................................... Document #: 0.2 Page 2 of 14
Pin Definitions
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, Access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h)
.
Pin No.
Name
Type
Description
1
VDD
PWR 3.3V Power supply
2
SDATA
I/O
SMBus compatible SDATA.
3
SCLK
I
SMBus compatible SCLOCK.
4
VDD
PWR 3.3V power supply
5
VSS
GND
Ground
6
VDD
PWR 3.3V power supply
7
VSS
GND
Ground
8
SRC1
O, DIF 100 MHz Differential serial reference clocks.
9
SRC1#
O, DIF 100 MHz Differential serial reference clocks.
10
VSS
GND
Ground
11
SRC2
O, DIF 100 MHz Differential serial reference clocks.
12
SRC2#
O, DIF 100 MHz Differential serial reference clocks.
13
VDD
PWR 3.3V power supply
14
VDD
PWR 3.3V power supply
15
VSS
GND
Ground
16
VDD
PWR 3.3V power supply
17
SSON
I
3.3V LVTTL input for enabling spread spectrum clock
0 = Disable, 1 = Enable (-0.5% SS)
External 10K ohm pull-up or pull-down resistor required
18
VSS
GND
Ground
19
XOUT
O, SE 14.318 MHz Crystal output.
20
XIN
I
14.318 MHz Crystal input.
Table 1. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SL28SRC02BZIT | 功能描述:时钟发生器及支持产品 PCIE Clk Gen Xin 14M -->4 PCIE out Gen3 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SL28SRC02BZITR | 制造商:Silicon Laboratories Inc 功能描述: |
| SL28SRC04BZC | 功能描述:时钟发生器及支持产品 PCIE Clk Gen 14.318M Xin 4PCIE out Gen3 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SL28SRC04BZCT | 功能描述:时钟发生器及支持产品 PCIE Clk Gen 14.318M Xin 4PCIE out Gen3 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SL28SRC04BZI | 功能描述:时钟发生器及支持产品 PCIE Clk Gen 14.318M Xin 2PCIE out Gen3 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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