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参数资料
| 型号： | SL28SRC04BZCT |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 13/13页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK 4PCIE GEN3 20TSSOP |
| 标准包装： | 2,000 |
| 类型： | * |
| PLL： | 是 |
| 输入： | 时钟，晶体 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:4 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 100MHz |
| 除法器/乘法器： | 无/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
SL28SRC04
............... Document #: SP-AP-0757 (Rev. 0.2) Page 9 of 13
Note 1: SRC bank one (SRC1,2) and SRC bank two (SRC3,4) are not synchronized.
AC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
SRC
TDC
SRC Duty Cycle
Measured at 0V differential
45
55
%
TPERIOD
100 MHz SRC Period
Measured at 0V differential @ 0.1s
9.99900
10.0010
ns
TPERIODSS
100 MHz SRC Period, SSC
Measured at 0V differential @ 0.1s
10.02406
10.02607
ns
TPERIODAbs
100 MHz SRC Absolute Period
Measured at 0V differential @ 1 clock
9.87400
10.1260
ns
TPERIODSSAbs 100 MHz SRC Absolute Period, SSC
Measured at 0V differential @ 1 clock
9.87406
10.1762
ns
TSKEW1
SRC1 to SRC2 or SRC3 to SRC4
Measured at 0V differential
100
ps
TCCJ
SRC Cycle to Cycle Jitter
Measured at 0V differential
–
50
ps
RMSGEN1
Output PCIe* Gen1 REFCLK phase
jitter
BER = 1E-12 (including PLL BW 8 - 16
MHz, ζ = 0.54, Td=10 ns,
Ftrk=1.5 MHz)
0108
ps
RMSGEN2
Output PCIe* Gen2 REFCLK phase
jitter
Includes PLL BW 8 - 16 MHz, Jitter
Peaking = 3dB, ζ = 0.54, Td=10 ns),
Low Band, F < 1.5MHz
03.0
ps
RMSGEN2
Output PCIe* Gen2 REFCLK phase
jitter
Includes PLL BW 8 - 16 MHz, Jitter
Peaking = 3dB, ζ = 0.54, Td=10 ns),
Low Band, F < 1.5MHz
03.1
ps
RMSGEN3
Output phase jitter impact – PCIe*
Gen3
Includes PLL BW 2 - 4 MHz,
CDR = 10MHz)
01.0
ps
LACC
SRC Long Term Accuracy
Measured at 0V differential
–
100
ppm
TR / TF
SRC Rising/Falling Slew Rate
Measured differentially from ±150 mV
2.5
8
V/ns
TRFM
Rise/Fall Matching
Measured single-endedly from ±75 mV
–
20
%
VHIGH
Voltage High
1.15
V
VLOW
Voltage Low
–0.3
–
V
VOX
Crossing Point Voltage at 0.7V Swing
300
550
mV
Tjphasepll
Phase Jitter
(PLL BW 8-16MHz, 5-16MHz)
RMS value
3.1
pS
ENABLE/DISABLE and SET-UP
TSTABLE
Clock Stabilization from Power-up
–
1.8
ms
TSS
Stopclock Set-up Time
10.0
–
ns
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