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参数资料
| 型号： | SLO2016 |
| 元件分类： | 显示用LED |
| 英文描述： | 5X7 DOT MATRIX DISPLAY, SUPER RED, 4.57 mm |
| 封装： | ROHS COMPLIANT PACKAGE-14 |
| 文件页数： | 5/10页 |
| 文件大小： | 437K |
| 代理商： | SLO2016 |
SLR2016, SLO2016, SLG2016, SLY2016, SCD5584A
2006-01-23
4
Timing Characteristics—Write Cycle Waveforms
Loading Data
The desired data code (D0–D6) and digit address (A0, A1) must
be held stable during the write cycle for storing new data.
Data entry may be asynchronous. Digit 0 is defined as right hand
digit with A1=A2=0.
Clearing the entire internal four-digit memory can be accomplished
by holding the clear (CLR) low for 1.0 msec minimum. The clear
function will clear the ASCII RAM. Loading an illegal data code will
display a blank.
Pin Function
Pin
Function
Pin
Function
1
WR Write
8
D3 Data
2
A1 Digit Select
9
D4 Data
3
A0 Digit Select
10
D5 Data
4
V
CC
11
D6 Data
5
D0 Data
12
BL Display Blank
6
D1 Data
13
CLR Clear
7
D2 Data
14
GND
Pin Function
Pin
Function
Pin
Function
DC Characteristics at 25°C
Parameters
Min.
Typ.
Max.
Units
Conditions
V
CC
4.5
5.0
5.5
V
—
ICC Blank
—
2.3
3.0
mA
V
CC=5.0 V
ICC (80 dots on)
—
80
105
mA
V
CC=5.0 V
VIL (all inputs)
—
0.8
V
4.5 V <V
CC <5.5 V
VIH (all inputs)
2.0
—
V
4.5 V <V
CC <5.5 V
IIL (all inputs)
25
—
100
A
4.5 V <V
CC <5.5 V, VIN=0.8 V
AC Characteristics (guaranteed minimum timing
parameters at V
CC=5.0 V ±0.5 V)
Parameter
Symbol
–40°C
+25°C
+85°C
Unit
Address Set
Up Time
TAS
10
ns
Write Time
TW
60
70
90
ns
Data Set Up
Time
TDS
20
30
50
ns
Address Hold
Time
TAH
20
30
40
ns
Data Hold
Time
TDH
20
30
40
ns
Access Time
TACC
(1)
90
110
140
ns
Clear Disable
Time
TCLRD
1.0
s
Clear Time
TCLR
1.0
ms
Note:
1) T
ACC=Set Up Time + Write Time + Hold Time
TAS
TDH
TAH
TDS
TACC
TW
WR
CLR
A0 – A1
D0 – D6
2.0 V
0.8 V
2.0 V
0.8 V
2.0 V
0.8 V
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