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参数资料
| 型号： | SM320C2550GBM |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 16-BIT, 50 MHz, OTHER DSP, CPGA68 |
| 封装： | CERAMIC, MO-067AA, MO-066AA, PGA-68 |
| 文件页数： | 14/40页 |
| 文件大小： | 681K |
| 代理商： | SM320C2550GBM |
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SMJ320C25, SMJ320C2550
DIGITAL SIGNAL PROCESSOR
SGUS007D – AUGUST 1988 – REVISED OCTOBER 2001
21
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
RS, INT, BIO, and XF timing
switching characteristics over recommended operating conditions (see Note 1)
PARAMETER
SMJ320C25-50
SMJ320C25
UNIT
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
td(RS)
Delay time, CLKOUT1 low to reset state entered
22
ns
td(IACK) Delay time, CLKOUT1 to IACK valid
–5
0
7
–8
0
8
ns
td(XF)
Delay time, XF valid before falling edge of STRB
Q – 10
Q – 12
ns
timing requirements over recommended operating conditions (see Note 1)
SMJ320C25-50
SMJ320C25
UNIT
MIN
MAX
MIN
MAX
UNIT
tsu(IN)
Setup time, INT/BIO/RS before CLKOUT1 high
25
32
ns
th(IN)
Hold time, INT/BIO/RS after CLKOUT1 high
0
ns
tw(IN)
Pulse duration, INT/BIO low
tc(C)
ns
tw(RS)
Pulse duration, RS low
3tc(C)
ns
switching characteristics over recommended operating conditions (see Note 1)
PARAMETER
SMJ320C25-50
SMJ320C25
UNIT
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
td(C1L-AL) Delay time, HOLDA low after CLKOUT1 low
–1
11
–1
10
ns
tdis(AL-A) Disable time, HOLDA low to address three-state
0
ns
tdis(C1L-A)
Disable time, address three-state after CLKOUT1 low (HOLD
mode, see Note 7 )
20
ns
td(HH-AH) Delay time, HOLD high to HOLDA high
19
25
ns
ten(A-C1L)
Enable time, address driven before CLKOUT1 low (HOLD mode,
see Note 7 )
8
ns
timing requirements over recommended operating conditions (see Note 1)
SMJ320C25-50
SMJ320C25
UNIT
MIN
MAX
MIN
MAX
UNIT
td(C2H-H) Delay time, HOLD valid after CLKOUT2 high
Q – 19
Q – 24
ns
These values are derived from characterization data and not tested.
NOTES:
1. Q = 1/4tc(C)
6. RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is
met, the exact sequence shown in the timing diagram occurs. INT/BIO fall time must be less than 8 ns.
7. A15–A0, PS, DS, IS, STRB, and R/W timings are all included in timings referenced as ’”address”.
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