参数资料
| 型号： | SM843256KA TR |
| 厂商： | Micrel Inc |
| 文件页数： | 5/8页 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER LVPECL 24TSSOP |
| 产品培训模块： | High Bandwidth Product Overview |
| 标准包装： | 2,500 |
| 系列： | RotaryWave™ |
| 类型： | 时钟/频率合成器，扇出配送，多路复用器 |
| PLL： | 带旁路 |
| 输入： | 晶体 |
| 输出： | LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:6 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 625MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 供应商设备封装： | 24-TSSOP 裸露焊盘 |
| 包装： | 带卷 (TR) |
Micrel, Inc.
SM843256
July 2010
5
M9999-072110-B
LVPECL DC Electrical Characteristics
(5, 6)
VDDA = VDD = 3.3V ±5% or 2.5V ±5%, VDDO = 2.5V or 3.3V ±5%, TA = –40°C to +85°C, unless noted.
Symbol
Parameter
Condition
Min
Typ
Max
Units
VOH
Output High Voltage
50 to VDDO-2V
VDDO
–1.145
VDDO
–0.97
VDDO
–0.845
V
VOL
Output Low Voltage
50 to VDDO-2V
VDDO
–1.945
VDDO
–1.77
VDDO
–1.645
V
VSWING
Peak-to-Peak Output Voltage Swing
Figure 1
0.6
0.8
1.0
V
LVCMOS DC Electrical Characteristics
(6)
VDDA = VDD = 3.3V ±5% or 2.5V ±5%, VDDO = 2.5V or 3.3V ±5%, TA = –40°C to +85°C, unless noted.
Symbol
Parameter
Condition
Min
Typ
Max
Units
VIH
Input High Voltage
2
VDD
+0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
Input High Current (FB_SEL)
VDD = VIN = 3.465V
150
μA
IIH
Input High Current (PLL_BYPASS),
(N_SEL0), (NSEL1)
VDD = VIN = 3.465V
5
μA
IIL
Input Low Current (FB_SEL)
VDD = 3.465V, VIN = 0V
-5
μA
IIL
Input Low Current (PLL_BYPASS),
(N_SEL0), (NSEL1)
VDD = 3.465V, VIN = 0V
-150
μA
AC Electrical Characteristics
(7)
VDDA = VDD = 3.3V ±5% or 2.5V ±5%, VDDO = 2.5V or 3.3V ±5%, TA = –40°C to +85°C, unless noted.
Symbol
Parameter
Condition
Min
Typ
Max
Units
FOUT
Output Frequency
Refer to Frequency Table
75
625
MHz
TR/TF
LVPECL Output Rise/Fall Time
20% – 80%
100
175
350
ps
ODC
Output Duty Cycle
46
50
54
%
TSKEW
Output-to-Output Skew
Note 8
45
ps
TLOCK
PLL Lock Time
20
ms
Integration Range (12kHz – 20MHz)
251
fs
Tjit()
RMS Phase Jitter (Output = 156.25 MHz)
Integration Range (1.875MHz – 20MHz)
80
fs
Notes:
5. See Figure 4 for load test circuit example.
6. The circuit is designed to meet the DC specifications shown in the above table(s) after thermal equilibrium has been established.
7. The circuit is designed to meet the AC specifications shown in the above table(s) after thermal equilibrium has been established.
8. Defined as skew between outputs at the same supply voltage and with equal load conditions; Measured at the output differential crossing points.
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