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参数资料
| 型号： | SMS64FR08 |
| 厂商： | Summit Microelectronics, Inc. |
| 英文描述： | Six-Channel Supply Monitor and Sequencing Controller |
| 中文描述： | 6通道电源监视器和排序控制器 |
| 文件页数： | 5/24页 |
| 文件大小： | 647K |
| 代理商： | SMS64FR08 |
SMS64
Preliminary
Summit Microelectronics, Inc
2060 2.22 10/09/03
5
Pin
Number
Pin
Type
Pin Name
Pin Description
24
PWR
GND
GND is the ground for both the analog and digital portions of the internal
circuitry. It is internally tied to pin 15. (Both pins should be tied to system ground).
The interrupt output is an active low open-drain output. It will be driven low
whenever the Watchdog timer times out or whenever an enabled under-voltage or
over-voltage condition on a VM input exists.
The IRQ# signal is held in an inactive state during the power-on and
power-off sequence.
During the power-on sequence RST_B# will be asserted (driven low) until the
entire power-on sequence has been completed and the programmable reset
interval timer (tPRTO) has elapsed.
RST_B# will be forced low by asserting the MR# input. It will remain low so long
as the MR# input is low plus the programmed reset time out period for RST_B#.
RST_B# will be asserted whenever an enabled UV/OV condition exists.
RST_B# will remain active so long as the UV/OV condition exists and t
PRTO
expires.
The RST_B# is an active low open drain output.
During the power-on sequence RST_A# will be driven low and will remain low
until a selected PUP output has become active. and the triggers for RST_A# are
inactive. In this manner the RST_A# can be used to release a portion of the circuitry
from reset before the entire system is energized.
RST_A# will be forced low by asserting the MR# input. It will remain low so long
as the MR# input is low plus the programmed reset time out period for RST_A#.
RST_A# will be asserted whenever an enabled UV/OV condition exists.
RST_A# will remain active so long as the UV/OV condition exists and t
PRTO
expires.
The RST_A# is an active low open drain output.
The healthy output is used to signal that the VM inputs are not generating any
under-voltage or over-voltage conditions.
WLDI is the Watchdog and Longdog timers’ interrupt input. A low to high
transition on the WLDI input will clear both the Watchdog and Longdog timers,
effectively starting a new time-out period.
If WLDI is stuck low and no low-to-high transition is received within the
programmed t
PWDTO
period (programmed watch dog time-out) IRQ# will be driven
low. If a transition is still not received within the programmed t
PLDTO
period
(programmed Longdog time-out) RESET# will be driven low. Refer to Figure 5 for a
detailed illustration.
Holding WLDI high will block interrupts from occurring but will not block the
Longdog from timing out and generating a reset. Refer to Figure 3 for a detailed
illustration of the relationship between IRQ#, RESET#, and WLDI.
25
O
IRQ#
26
O
RST_B#
27
O
RST_A#
28
O
HEALTHY#
30
I
WLDI
31
32
33
34
35
36
I
I
I
I
I
I
VM
A
VM
B
VM
C
VM
D
VM
E
VM
F
The VM pins are the voltage monitor inputs. The input voltage is either
compared to a programmed threshold voltage (V
PTH
) or it can be compared to a
preset reference voltage of 0.5V.
PIN DESCRIPTIONS CONT’D
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