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参数资料
| 型号： | SN54ACT11109FK |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 锁存器 |
| 英文描述： | ACT SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20 |
| 封装： | LCC-20 |
| 文件页数： | 1/5页 |
| 文件大小： | 70K |
| 代理商： | SN54ACT11109FK |
54ACT11109, 74ACT11109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS451 – FEBRUARY 1987 – REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1993, Texas Instruments Incorporated
2–1
Inputs Are TTL-Voltage Compatible
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V
CC and GND Configurations
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-
m Process
500-mA Typical Latch-Up Immunity
at 125
°C
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and
Ceramic 300-mil DIPs
description
These devices contain two independent J-K
positive-edge-triggered flip-flops. A low level at
the preset (1PRE or 2PRE) or clear (1CLR or
2CLR) input sets or resets the outputs regardless
of the levels of the other inputs. When PRE and
CLR are inactive (high), data at the J and K inputs
meeting
the
setup
time
requirements
are
transferred to the outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at
a voltage level and is not directly related to the rise
time of the clock pulse. Following the hold-time
interval, data at the J and K inputs may be
changed without affecting the levels at the
outputs. These versatile flip-flops can perform as
toggle flip-flops by grounding K and tying J high.
They also can perform as D-type flip-flops if J and
K are tied together.
The 54ACT11109 is characterized for operation over the full military temperature range of – 55
°C to 125°C. The
74ACT11109 is characterized for operation from – 40
°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
J
K
Q
L
H
X
H
L
H
LX
X
L
H
L
LX
X
H
↑
LL
L
H
↑
H
L
Toggle
H
↑
LH
Q0
H
↑
HH
H
L
H
L
X
Q0
This configuration is nonstable; that is, it will not persist when
either PRE or CLR returns to the inactive (high) level.
54ACT11109 ...J PACKAGE
74ACT11109 ...D OR N PACKAGE
(TOP VIEW)
54ACT11109 . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1PRE
1Q
GND
2Q
2PRE
2CLK
1CLK
1K
1J
1CLR
VCC
2CLR
2J
2K
3
2
1 20 19
910 11 12 13
4
5
6
7
8
18
17
16
15
14
2J
2K
NC
2CLK
2PRE
1K
1CLK
NC
1PRE
1Q
1J
NC
2Q
2CLR
1Q
GND
NC
CC
V
1CLR
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SN54ACT11FK | 制造商:TI 制造商全称:Texas Instruments 功能描述:TRIPLE 3-INPUT POSITIVE-AND GATES |
| SN54ACT11J | 制造商:TI 制造商全称:Texas Instruments 功能描述:TRIPLE 3-INPUT POSITIVE-AND GATES |
| SN54ACT11W | 制造商:TI 制造商全称:Texas Instruments 功能描述:TRIPLE 3-INPUT POSITIVE-AND GATES |
| SN54ACT1284 | 制造商:TI 制造商全称:Texas Instruments 功能描述:7-BIT BUS INTERFACES WITH 3-STATE OUTPUTS |
| SN54ACT1284FK | 制造商:TI 制造商全称:Texas Instruments 功能描述:7-BIT BUS INTERFACES WITH 3-STATE OUTPUTS |
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