SN54ALS137, SN74ALS137A
SN54AS137, SN74AS137
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES
SDAS203B – APRIL 1982 – REVISED DECEMBER 1994
Copyright
1994, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Combines Decoder and 3-Bit Address
Latch
Incorporates Two Output Enables to
Simplify Cascading
Package Options Include Plastic Small-
Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
The SN54ALS137, SN74ALS137A, and
′AS137
are 3-line to 8-line decoders/demultiplexers with
latches on the three address inputs. When the
latch-enable (LE) input is low, the SN54ALS137,
SN74ALS137A,
and
′AS137
act
as
a
decoder/demultiplexer. When LE goes from low to
high, the address present at the select (A, B, and
C) inputs is stored in the latches. Further address
changes are ignored as long as LE remains high.
The output-enable (OE1 and OE2) inputs control
the outputs independently of the select or
latch-enable inputs. All of the outputs are forced
high if OE1 is low or OE2 is high. The
SN54ALS137, SN74ALS137A, and
′AS137 are
ideally
suited
for
implementing
glitch-free
decoders in strobed (stored-address) applications
in bus-oriented systems.
The
SN54ALS137
and
SN54AS137
are
characterized for operation over the full military
temperature range of – 55
°C to 125°C. The
SN74ALS137A
and
SN74AS137
are
characterized for operation from 0
°C to 70°C.
logic symbols (alternatives)
X/Y
1
A
2
B
3
C
C8
4
5
6
OE1
Y0
15
0
&
EN
Y1
14
1
Y2
13
2
Y3
12
3
Y4
11
4
Y5
10
5
Y6
9
6
Y7
7
G
7
0
LE
OE2
8D
1
2
4
DMUX
1
A
2
B
3
C
C8
4
5
6
OE1
Y0
15
0
&
Y1
14
1
Y2
13
2
Y3
12
3
Y4
11
4
Y5
10
5
Y6
9
6
Y7
7
LE
OE2
8D
0
2
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
SN54ALS137, SN54AS137 ...J PACKAGE
SN74ALS137A, SN74AS137 ...D OR N PACKAGE
(TOP VIEW)
3
2
1 20 19
910 11 12 13
4
5
6
7
8
18
17
16
15
14
Y1
Y2
NC
Y3
Y4
C
LE
NC
OE2
OE1
SN54ALS137, SN54AS137 . . . FK PACKAGE
(TOP VIEW)
B
A
NC
Y6
Y5
Y0
Y7
GND
NC
NC – No internal connection
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A
B
C
LE
OE2
OE1
Y7
GND
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.