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参数资料
| 型号： | SN54HC112WR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 锁存器 |
| 英文描述： | HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16 |
| 封装： | CERAMIC, FP-16 |
| 文件页数： | 6/7页 |
| 文件大小： | 94K |
| 代理商： | SN54HC112WR |
SN54HC112, SN74HC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS099C – DECEMBER 1982 – REVISED APRIL 1999
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
th
tsu
50%
10%
90%
VCC
0 V
tr
tf
Reference
Input
Data
Input
50%
High-Level
Pulse
50%
VCC
0 V
50%
VCC
0 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
10%
90%
VCC
VOH
VOL
0 V
tr
tf
Input
In-Phase
Output
50%
tPLH
tPHL
50%
10%
90%
VOH
VOL
tr
tf
tPHL
tPLH
Out-of-Phase
Output
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
≤ 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Figure 1. Load Circuit and Voltage Waveforms
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