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参数资料
| 型号： | SN54HC289 |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | 8-BIT ADDRESSABLE LATCHES |
| 中文描述： | 8位可寻址锁存器 |
| 文件页数： | 2/15页 |
| 文件大小： | 341K |
| 代理商： | SN54HC289 |
SCLS134E DECEMBER 1982 REVISED SEPTEMBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs. In the
addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch
follows the data input, with all unaddressed latches remaining in their previous states. In the memory mode, all
latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the
possibility of entering erroneous data in the latches, G should be held high (inactive) while the address lines
are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the level of the
D input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data
inputs.
Function Tables
FUNCTION
INPUTS
OUTPUT OF
ADDRESSED
LATCH
EACH
OTHER
OUTPUT
FUNCTION
CLR
G
H
L
D
QiO
QiO
L
Addressable latch
H
H
QiO
D
Memory
L
L
8-line demultiplexer
L
H
L
L
Clear
LATCH SELECTION
SELECT INPUTS
S2
S1
LATCH
ADDRESSED
S0
L
L
L
0
L
L
H
1
L
H
L
2
L
H
H
3
H
L
L
4
H
L
H
5
H
H
L
6
H
H
H
7
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