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参数资料
| 型号： | SN54LS192J |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 计数器 |
| 英文描述： | LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, CDIP16 |
| 封装： | CERAMIC, DIP-16 |
| 文件页数： | 6/15页 |
| 文件大小： | 511K |
| 代理商： | SN54LS192J |
Product Folder: SN54192, Synchronous 4-Bit Up/Down Counters (Dual Clock With Clear)
Keyword
Part Number
PRODUCT SUPPORT: TRAINING
SN54192, Synchronous 4-Bit Up/Down Counters (Dual Clock With Clear)
DEVICE STATUS: ACTIVE
PARAMETER NAME SN54192
Voltage Nodes (V) 5
Vcc range (V)
4.5 to 5.5
Input Level
TTL
Output Level
TTL
Output
2S
Clear
Async
FEATURES
q
Cascading Circuitry Provided Internally
q
Synchronous Operation
q
Individual Preset to Each Flip-Flop
q
Fully Independent Clear Input
DESCRIPTION
These monolithic circuits are synchronous reversible (up/down) counters having a complexity of 55 equivalent gates. The '192 and 'LS192 circuits are BCD counters and the '193 and 'LS193 are 4-bit binary
counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidently with each other when so instructed by the steering logic. This mode of
operation eliminates the output counting spikes which are normally associated with asynchronous (ripple-clock) counters.
The outputs of the four master-slave flip-flops are triggered by a low-to-high-level transition of either count (clock) input. The direction of counting is determined by which count input is pulsed while the other
count input is high.
All four counters are fully programmable; that is, each output may be preset to either level by entering the desired data at the data inputs while the load input is low. The output will change to agree with the
data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs.
A clear input has been provided which forces all outputs to the low level when a high level is applied. The clear function is independent of the count and load inputs. The clear, count, and load inputs are
buffered to lower the drive requirements. This reduces the number of clock drivers etc., required for long words.
These counters are designed to be cascaded without the need for external circuitry. Both borrow and carry outputs are available to cascade both the up- and down-counting functions. The borrow output
produces a pulse equal in width to the count-down input when the counter underflows. Similarly, the carry output produces a pulse equal in width to the count-up input when an overflow condition exists. The
counters can then be easily cascaded by feeding the borrow and carry outputs to the count-down and count-up inputs respectively of the succeeding counter.
TECHNICAL DOCUMENTS
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DATASHEET
APPLICATION NOTES
View Application Notes for Digital Logic
file:///E|/042120003_HTML/sn54192.html (1 of 2) [25-Apr-03 2:22:47 PM]
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SN54LS193J | 制造商:Texas Instruments 功能描述:Counter Single 4-Bit Binary UP/Down 16-Pin CDIP Tube 制造商:Texas Instruments 功能描述:SYNC UP/DOWN BINARY COUNTER 制造商:Texas Instruments 功能描述:COUNTER SGL 4BIT BINARY UP/DOWN 16CDIP - Rail/Tube |
| SN54LS194AJ | 制造商:Texas Instruments 功能描述:Shift Register Single 4-Bit Serial/Parallel to Parallel 16-Pin CDIP Tube 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:SHIFT REGISTER SGL 4BIT SERL/PARALLEL TO PARALLEL 16CDIP - Rail/Tube |
| SN54LS194AW | 制造商:Texas Instruments 功能描述: |
| SN54LS195AJ | 制造商:Texas Instruments 功能描述: 制造商:Texas Instruments 功能描述:4-BIT SHIFT REGISTER - Rail/Tube |
| SN54LS197J | 制造商:Texas Instruments 功能描述: |
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