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参数资料
| 型号： | SN54LS273J |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 锁存器 |
| 英文描述： | LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP20 |
| 封装： | 0.300 INCH, CERAMIC, DIP-20 |
| 文件页数： | 2/3页 |
| 文件大小： | 63K |
| 代理商： | SN54LS273J |
5-2
FAST AND LS TTL DATA
SN54/74LS273
FUNCTIONAL DESCRIPTION
The SN54 / 74LS273 is an 8-Bit Parallel Register with a
common Clock and common Master Reset.
When the MR input is LOW, the Q outputs are LOW,
independent of the other inputs. Information meeting the setup
and hold time requirements of the D inputs is transferred to the
Q outputs on the LOW-to-HIGH transition of the clock input.
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
–55
0
25
125
70
°C
IOH
Output Current — High
54, 74
– 0.4
mA
IOL
Output Current — Low
54
74
4.0
8.0
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Sb l
P
Limits
Ui
T
C
di i
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54
0.7
V
Guaranteed Input LOW Voltage for
VIL
Input LOW Voltage
74
0.8
V
pg
All Inputs
VIK
Input Clamp Diode Voltage
– 0.65
– 1.5
V
VCC = MIN, IIN = – 18 mA
VOH
Output HIGH Voltage
54
2.5
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
VOH
Output HIGH Voltage
74
2.7
3.5
V
CC
, OH
,
IN
IH
or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
0.25
0.4
V
IOL = 4.0 mA
VCC = VCC MIN,
VIN =VIL or VIH
VOL
Output LOW Voltage
74
0.35
0.5
V
IOL = 8.0 mA
VIN = VIL or VIH
per Truth Table
IIH
Input HIGH Current
20
A
VCC = MAX, VIN = 2.7 V
IIH
Input HIGH Current
0.1
mA
VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
– 0.4
mA
VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 1)
–20
– 100
mA
VCC = MAX
ICC
Power Supply Current
27
mA
VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Sb l
P
Limits
Ui
T
C
di i
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
fMAX
Maximum Input Clock Frequency
30
40
MHz
Figure 1
tPHL
Propagation Delay, MR to Q Output
18
27
ns
Figure 2
tPLH
tPHL
Propagation Delay, Clock to Output
17
18
27
ns
Figure 1
相关PDF资料 |
PDF描述 |
|---|---|
| SN54LS273W883B | D FLIP-FLOP, CDFP20 |
| SN54LS273W | D FLIP-FLOP, CDFP20 |
| SN54LS273F | D FLIP-FLOP, MQFP20 |
| SN74S273N | D FLIP-FLOP, PDIP20 |
| SN54S273L883B | D FLIP-FLOP, MQCC20 |
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