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参数资料
| 型号： | SN54LS569AJ |
| 厂商： | MOTOROLA INC |
| 元件分类： | 计数器 |
| 英文描述： | LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, CDIP20 |
| 封装： | 732-03 |
| 文件页数： | 2/6页 |
| 文件大小： | 107K |
| 代理商： | SN54LS569AJ |
5-2
FAST AND LS TTL DATA
SN54/74LS569A
FUNCTION TABLE
INPUTS
OUTPUTS
CP
D
C
B
A
LOAD
CET
CEP
U/D
ACLR
SCLR
OE
RCO
CCO
YD
YC
YB
YA
↑
X
H
L
H
L
A/R
(QT – CP) + 1
Count Up
↑
X
XX
X
H
L
H
L
A/R
(QT – CP) – 1
Count Down
↑
X
XX
X
H
X
H
L
H
NC
Count Inhibit
↑
X
XX
X
H
L
H
X
H
L
A/R
H
NC
Count Inhibit
X
L
H
L
H
Overflow
↑
X
XX
X
L
H
L
H
Overflow
↑
X
XX
X
H
X
H
L
H
Overflow Inhibit
X
XX
X
L
H
L
Underflow
↑
X
XX
X
L
H
L
H
L
H
L
Underflow
↑
X
XX
X
H
X
L
H
L
H
L
Underflow Inhibit
↑
L
H
L
H
L
X
H
L
H
L
H
L
H
Load Example
↑
X
XX
X
H
X
H
L
H
L
Clear (Synchronous)
X
XX
X
L
H
L
Clear (Synchronous)
↑
X
XX
X
L
H
L
H
L
H
L
Clear (Synchronous)
↑
X
XX
X
H
X
L
H
L
H
L
Clear (Synchronous)
X
XX
X
H
L
X
L
H
L
Asynchronous Clear
X
XX
X
L
X
L
Asynchronous Clear
X
XX
X
L
H
L
X
L
H
L
Asynchronous Clear
X
XX
X
H
X
L
X
L
H
L
Asynchronous Clear
X
H
X
Hi-Z
Output Disabled
(QT — CP) = Output state prior to clock edge
A/R = Assumes required output state;
X = Don’t care
NC = No change
High except during Overflow and Underflow
LOGIC DIAGRAM
OE
ACLR
A
B
C
SCLR
LOAD
CEP
CET
CP
U/D
YA
YB
YC
YD
RCO
CCO
*
D
R
CP
Q
*
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