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参数资料
| 型号： | SN54LV74FK |
| 厂商： | Texas Instruments, Inc. |
| 元件分类： | 通用总线功能 |
| 英文描述： | Dual 4-Stage Binary Ripple Counter with Divide-By-2 and Divide-By-5 Sections; Package: TSSOP-16; No of Pins: 16; Container: Tape and Reel; Qty per Container: 2500 |
| 中文描述： | 双上升沿触发的D型触发器 |
| 文件页数： | 4/7页 |
| 文件大小： | 137K |
| 代理商： | SN54LV74FK |
SN54LV74, SN74LV74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
SN54LV74
SN74LV74
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
IOH = –100
μ
A
IOH = –6 mA
IOH = –12 mA
IOL = 100
μ
A
IOL = 6 mA
IOL = 12 mA
MIN to MAX
VCC – 0.2
2.4
VCC – 0.2
2.4
VOH
3 V
V
4.5 V
3.6
3.6
MIN to MAX
0.2
0.2
VOL
3 V
0.4
0.4
V
4.5 V
0.55
±
1
±
1
20
0.55
±
1
±
1
20
II
VI= VCCor GND
VI = VCC or GND
3.6 V
μ
A
5.5 V
ICC
VI= VCCor GND
VI = VCC or GND
IO= 0
IO = 0
3.6 V
μ
A
5.5 V
20
20
ICC
One input at
VCC – 0.6 V
Other inputs at
VCC or GND
3 V to 3.6 V
500
500
μ
A
Ci
VI= VCCor GND
VI = VCC or GND
3.3 V
2.5
2.5
pF
5 V
3
3
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN54LV74
VCC = 3.3 V
±
0.3 V
VCC = 5 V
±
0.5 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
fclock
Clock frequency
0
70
0
60
0
50
ns
tw
Pulse duration LE high
Pulse duration, LE high
PRE or CLR low
15
20
25
ns
CLK high or low
15
20
25
tsu
Setup time data before CLK
↑
Setup time, data before CLK
Data
6
8
12
ns
PRE or CLR inactive
5
6
8
th
Hold time, data after CLK
↑
3
3
3
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN74LV74
VCC = 3.3 V
±
0.3 V
VCC = 5 V
±
0.5 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
fclock
Clock frequency
0
70
0
60
0
50
ns
tw
Pulse duration LE high
Pulse duration, LE high
PRE or CLR low
15
20
25
ns
CLK high or low
15
20
25
tsu
Setup time data before CLK
Setup time, data before CLK
↑
Data
6
8
12
ns
PRE or CLR inactive
5
6
8
th
Hold time, data after CLK
↑
3
3
3
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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