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参数资料
| 型号： | SN54LVTH162373WDR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 总线收发器 |
| 英文描述： | LVT SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, CDFP48 |
| 封装： | 0.380 INCH, CERAMIC, PACKAGE-48 |
| 文件页数： | 1/8页 |
| 文件大小： | 104K |
| 代理商： | SN54LVTH162373WDR |
SN54LVTH162373, SN74LVTH162373
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS261J – JULY 1993 – REVISED APRIL 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Members of the Texas Instruments
Widebus
Family
D State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D Output Ports Have Equivalent 22- Series
Resistors, So No External Resistors Are
Required
D Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V VCC)
D Support Unregulated Battery Operation
Down to 2.7 V
D Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
D Ioff and Power-Up 3-State Support Hot
Insertion
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D Flow-Through Architecture Optimizes PCB
Layout
D Latch-Up Performance Exceeds 500 mA Per
JESD 17
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’LVTH162373 devices are16-bit transparent D-type latches with 3-state outputs designed for low-voltage
(3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These
devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and
working registers.
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up
at the D inputs.
Copyright
1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Widebus is a trademark of Texas Instruments Incorporated.
SN54LVTH162373 . . . WD PACKAGE
SN74LVTH162373 ... DGG OR DL PACKAGE
(TOP VIEW)
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1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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