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| 型号： | SN74ACT16374EPDLR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 总线收发器 |
| 英文描述： | ACT SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| 封装： | 0.300 INCH, PLASTIC, SSOP-48 |
| 文件页数： | 5/6页 |
| 文件大小： | 88K |
| 代理商： | SN74ACT16374EPDLR |
SN74ACT16374EP
16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS679 – MAY 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
1.5 V
3 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
tPLH
VOH
VOL
1.5 V
3 V
0 V
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
(see Note B)
50% VCC
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
× VCC
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
× VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
≈VCC
0 V
50% VCC
20% VCC
50% VCC
80% VCC
≈0 V
3 V
GND
Open
VOLTAGE WAVEFORMS
tPLH /tPHL
tPLZ /tPZL
tPHZ /tPZH
Open
2
× VCC
GND
TEST
S1
3 V
0 V
1.5 V
tw
VOLTAGE WAVEFORMS
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤ 1 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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