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参数资料
| 型号： | SN74ALVCHG162282GR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 总线收发器 |
| 英文描述： | ALVC/VCX/A SERIES, 18-BIT EXCHANGER, TRUE OUTPUT, PDSO80 |
| 封装： | GREEN, PLASTIC, TSSOP-80 |
| 文件页数： | 1/12页 |
| 文件大小： | 291K |
| 代理商： | SN74ALVCHG162282GR |
www.ti.com
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DESCRIPTION
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VCC
GND
2B9
1B9
2B8
GND
1B8
2B7
1B7
VCC
2B6
1B6
2B5
1B5
GND
2B4
1B4
2B3
1B3
VCC
GND
2B2
1B2
2B1
1B1
VCC
A1
A2
A3
GND
A4
A5
A6
VCC
A7
A8
A9
GND
CLK
SEL
VCC
GND
1B10
2B10
1B11
GND
2B11
1B12
2B12
VCC
1B13
2B13
1B14
2B14
GND
1B15
2B15
1B16
2B16
VCC
GND
1B17
2B17
1B18
2B18
VCC
A18
A17
A16
GND
A15
A14
A13
VCC
A12
A11
A10
GND
OE
DIR
DBB PACKAGE
(TOP VIEW)
SN74ALVCHG162282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES094D – FEBRUARY 1997 – REVISED OCTOBER 2004
Member of the Texas Instruments Widebus
Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
A-Port Outputs Have Equivalent 50-
Series
Resistors and B-Port Outputs Have Equivalent
20-
Series Resistors, So No External
Resistors Are Required
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Packaged in Thin Very Small-Outline Package
NOTE: For order entry, the DBB package is abbreviated to G. For
tape and reel, the DBBR package is abbreviated to GR.
The SN74ALVCHG162282 is an 18-bit to 36-bit
registered bus exchanger. This device is intended for
use in applications where data must be transferred
from
a
narrow
high-speed
bus
to
a
wide
lower-frequency bus. It is designed specifically for
low-voltage (3.3-V) VCC operation.
The device provides synchronous data exchange
between the two ports. Data is stored in the internal
registers on the low-to-high transition of the clock
(CLK) input. For data transfer in the B-to-A direction,
the select (SEL) input selects 1B or 2B data for the A
outputs.
For data transfer in the A-to-B direction, a two-stage
pipeline is provided in the 1B path, with a single
storage register in the 2B path. Data flow is controlled
by
the
active-low
output-enable
(OE)
and
direction-control (DIR) input. DIR is registered to
synchronize the bus direction changes with the clock.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 1997–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SN74ALVCHR162245DL | 功能描述:总线收发器 Tri-State 16-Bit Bus RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| SN74ALVCHR162245DLR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN74ALVCHR162269ADLR | 制造商:Texas Instruments 功能描述: |
| SN74ALVCHR162269DL | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| SN74ALVCHR162409DGGR | 制造商:Texas Instruments 功能描述: |
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