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3
2
5
8
1
1A
1B
GND
3
2
4
5
1
V
CC
V
CC
V
CC
1Y
1B
GND
1B
GND
2A
2Y
Seemechanicaldrawingsfordimensions.
2
5
3
4
8
2Y
2B
2A
2Y
2A
4
6
7
6
7
8
6
1
7
1A
DCTPACKAGE
(TOP VIEW)
DCUPACKAGE
(TOP VIEW)
YEP OR YZP PACKAGE
(BOTTOMVIEW)
1A
2B
DESCRIPTION/ORDERING INFORMATION
DUAL 2-INPUT POSITIVE-NAND GATE
SCES440B – MAY 2003 – REVISED JUNE 2006
Available in the Texas Instruments
±8-mA Output Drive at 1.8 V
NanoStar and NanoFree Packages
Latch-Up Performance Exceeds 100 mA Per
Optimized for 1.8-V Operation and Is 3.6-V I/O
JESD 78, Class II
Tolerant to Support Mixed-Mode Signal
ESD Protection Exceeds JESD 22
Operation
– 2000-V Human-Body Model (A114-A)
I
off Supports Partial-Power-Down Mode
– 200-V Machine Model (A115-A)
Operation
– 1000-V Charged-Device Model (C101)
Sub-1-V Operable
Max t
pd of 1.2 ns at 1.8 V
Low Power Consumption, 10
A at 1.8 V
This dual 2-input positive-NAND gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V
to 1.95-V VCC operation.
The SN74AUC2G00 performs the Boolean function Y = A
B or Y = A + B in positive logic.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(2)
NanoStar – WCSP (DSBGA)
Reel of 3000
SN74AUC2G00YEPR
0.23-mm Large Bump – YEP
_ _ _UA_
NanoFree – WCSP (DSBGA)
Reel of 3000
SN74AUC2G00YZPR
–40°C to 85°C
0.23-mm Large Bump – YZP (Pb-free)
SSOP – DCT
Reel of 3000
SN74AUC2G00DCTR
U00_
VSSOP – DCU
Reel of 3000
SN74AUC2G00DCUR
U00_
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2)
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 2003–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.