- 您现在的位置：买卖IC网 > PDF目录98107 > SN74AUP2G79DCUR (TEXAS INSTRUMENTS INC) AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO8 PDF资料下载
参数资料
| 型号： | SN74AUP2G79DCUR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 锁存器 |
| 英文描述： | AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO8 |
| 封装： | SSOP-8 |
| 文件页数： | 2/20页 |
| 文件大小： | 724K |
| 代理商： | SN74AUP2G79DCUR |
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
VCC = 1.2 V
± 0.1 V
VCC = 0.8 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
CL
VM
VI
V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
Output
Waveform 1
S1 at 2 xVCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
VOL + V
VOH - V
≈0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Control
VCC/2
tPLZ/tPZL
tPHZ/tPZH
2 x VCC
GND
TEST
S1
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
GND
5 k
2 x VCC
SCES755B – DECEMBER 2009 – REVISED MARCH 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the
output control.
C.
All input pulses are supplied by generators having the following characteristics: PRR
≤ 10 MHz, ZO = 50 , tr/tf = 3 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
tPLZ and tPHZ are the same as tdis.
F.
tPLH and tPHL are the same as tpd.
G.
All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
10
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP2G79
相关PDF资料 |
PDF描述 |
|---|---|
| SN74AUP2G80DCUR | AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO8 |
| SN74AUP2G80RSER | AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, QCC8 |
| SN74AUP3G06DCUR | AUP/ULP/V SERIES, TRIPLE 1-BIT DRIVER, INVERTED OUTPUT, PDSO8 |
| SN74AUP3G17YFPR | AUP/ULP/V SERIES, TRIPLE 1-INPUT INVERT GATE, PBGA8 |
| SN74AUP3G34RSER | AUP/ULP/V SERIES, TRIPLE 1-INPUT NON-INVERT GATE, QCC8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SN74AUP2G79DCUR | 制造商:Texas Instruments 功能描述:Flip-Flop Logic IC 制造商:Texas Instruments 功能描述:IC, D-TYPE FLIP FLOP DUAL, 4.3NS, US8-8 |
| SN74AUP2G79DQER | 功能描述:触发器 Low-Pwr Dual Pos- Edge-Trgd D-Type RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel |
| SN74AUP2G79RSER | 功能描述:触发器 Lo-Pwr Dual Pos-Edge Triggered D-Type RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel |
| SN74AUP2G79YFPR | 功能描述:触发器 Low-Pwr Dual Pos- Edge-Trgd D-Type RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel |
| SN74AUP2G80DCUR | 功能描述:触发器 Lo-Pwr Dual Pos-Edge Trgr DType Flip-Flop RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。