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参数资料
| 型号： | SN74AVCH1T45YEPR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 总线收发器 |
| 英文描述： | AVC SERIES, 1-BIT TRANSCEIVER, TRUE OUTPUT, BGA6 |
| 封装： | DSBGA-6 |
| 文件页数： | 7/24页 |
| 文件大小： | 458K |
| 代理商： | SN74AVCH1T45YEPR |
www.ti.com
APPLICATION INFORMATION
1
2
3
6
5
4
VCC1
VCC2
SYSTEM-1
SYSTEM-2
DIR CTRL
I/O-1
I/O-2
VCC2
STATE
DIR CTRL
I/O-1
DESCRIPTION
1
2
3
4
H
L
Out
HiZ
SYSTEM-1 data to SYSTEM-2
SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1
and I/O-2 are disabled. The bus-line state depends on bus hold.
DIR bit is flipped. I/O-1 and I/O02 still are disabled. The bus-line
state depends on bus hold.
I/O-2
HiZ
Out
In
HiZ
In
SYSTEM-2 data to SYSTEM-1
Enable Times
SN74AVCH1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES598C – JULY 2004 – REVISED OCTOBER 2005
Figure 13 shows the SN74AVCH1T45 being used in a bidirectional logic level-shifting application. Since the
SN74AVCH1T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid
bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
Figure 13. Bidirectional Logic Level-Shifting Application
Following is a sequence that illustrates data transmission from SYSTEM-1 to SYSTEM-2 and then from
SYSTEM-2 to SYSTEM-1.
Calculate the enable times for the SN74AVCH1T45 using the following formulas:
tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74AVCH1T45 initially is transmitting from A to B, then
the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B
port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
15
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SN74AVCH1T45YZPR | 功能描述:转换 - 电压电平 SnglBDualSplyBusTrns w/CnfgrbleVltg RoHS:否 制造商:Micrel 类型:CML/LVDS/LVPECL to LVCMOS/LVTTL 传播延迟时间:1.9 ns 电源电流:14 mA 电源电压-最大:3.6 V 电源电压-最小:3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MLF-8 |
| SN74AVCH20T245GR | 功能描述:转换 - 电压电平 20BDUALSplyBUSTrnsw/ CnfgrbleVltgTRNSLTN RoHS:否 制造商:Micrel 类型:CML/LVDS/LVPECL to LVCMOS/LVTTL 传播延迟时间:1.9 ns 电源电流:14 mA 电源电压-最大:3.6 V 电源电压-最小:3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MLF-8 |
| SN74AVCH20T245KR | 功能描述:总线收发器 20B DUAL SUPPLY Bus Transceiver RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| SN74AVCH20T245VR | 功能描述:转换 - 电压电平 20B DUAL SUPPLY Bus Transceiver RoHS:否 制造商:Micrel 类型:CML/LVDS/LVPECL to LVCMOS/LVTTL 传播延迟时间:1.9 ns 电源电流:14 mA 电源电压-最大:3.6 V 电源电压-最小:3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MLF-8 |
| SN74AVCH24T245GRGR | 功能描述:转换 - 电压电平 24B Dual-Supply Bus Trans RoHS:否 制造商:Micrel 类型:CML/LVDS/LVPECL to LVCMOS/LVTTL 传播延迟时间:1.9 ns 电源电流:14 mA 电源电压-最大:3.6 V 电源电压-最小:3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MLF-8 |
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