SN74GTLPH306
8-BIT LVTTL-TO-GTL+ BUS TRANSCEIVER
SCES284A – OCTOBER 1999 – REVISED DECEMBER 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Bidirectional Interface Between GTL+
Signal Levels and LVTTL Logic Levels
D Equivalent to ’245 Function
D LVTTL Interfaces Are 5-V Tolerant
D Medium-Drive GTL+ Outputs (50 mA)
D LVTTL Outputs (–24 mA/24 mA)
D GTL+ Rise and Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrity
D Ioff and Power-Up 3-State Support Hot
Insertion
D Bus Hold on A-Port Data Inputs
D Package Options Include Plastic
Small-Outline (DW), Thin Very
Small-Outline (DGV), and Thin Shrink
Small-Outline (PW) Packages
description
The SN74GTLPH306 is a medium-drive 8-bit bus transceiver that provides LVTTL-to-GTL+ and
GTL+-to-LVTTL signal-level translation. It is equivalent to the ’245 function. The device provides a high-speed
interface between cards operating at LVTTL-logic levels and a backplane operating at GTL+-signal levels.
High-speed (about two times faster than standard LVTTL or TTL) backplane operation is a direct result of
GTLP’s reduced output swing (<1 V), reduced input threshold levels, improved differential input, and output
edge control (OEC
). Improved GTLP OEC circuits minimize bus settling time and have been designed and
tested using several backplane models. The medium drive is suitable for driving double-terminated backplanes.
GTL+ is the Texas Instruments derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3.
The AC specification of the SN74GTLPH306 is given only at the preferred higher noise margin GTL+, but the
user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTL+ (VTT = 1.5 V
and VREF = 1 V) signal levels.
Normally, the B port operates at GTL or GTL+ levels, while the A-port and control inputs are compatible with
LVTTL logic levels and are 5-V tolerant. VREF is the reference input voltage for the B port.
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
The SN74GTLPH306 is characterized for operation from –40
°C to 85°C.
PRODUCT
PREVIEW
Copyright
1999, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DGV, DW, OR PW PACKAGE
(TOP VIEW)
OE
VCC
A1
A2
A3
A4
GND
A5
A6
A7
A8
GND
DIR
VREF
B1
B2
B3
B4
GND
B5
B6
B7
B8
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OEC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.