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参数资料
| 型号： | SN74HSTL162374 |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | 16-Bit Edge-Triggered D-Type Flip-Flops(16位边沿D触发器(三态输出)) |
| 中文描述： | 16位边沿触发D类正反器（16位边沿?触发器（三态输出）） |
| 文件页数： | 1/8页 |
| 文件大小： | 174K |
| 代理商： | SN74HSTL162374 |
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN74ALVCH162374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES092 – JANUARY 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Member of the Texas Instruments
Widebus
Family
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
Output Ports Have Equivalent 26-
Series
Resistors, So No External Resistors Are
Required
ESD Protection Exceeds 2000 V Per
MIL-STD-833, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 16-bit edge-triggered D-type flip-flop is
designed for 2.3-V to 3.6-V V
CC
operation.
The SN74ALVCH162374 is particularly suitable
for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers. It
can be used as two 8-bit flip-flops or one 16-bit
flip-flop. On the positive transition of the clock
(CLK) input, the Q outputs of the flip-flop take on
the logic levels set up at the data (D) inputs.
The output enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low
logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data
can be retained or new data can be entered while the outputs are in the high-impedance state.
The outputs, which are designed to sink up to 12 mA, include 26-
resistors to reduce overshoot and
undershoot.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162374 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the
same printed circuit board area.
The SN74ALVCH162374 is characterized for operation from –40
°
C to 85
°
C.
DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
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7
8
9
10
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12
13
14
15
16
17
18
19
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21
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23
24
48
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43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
V
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1CLK
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V
CC
2D5
2D6
GND
2D7
2D8
2CLK
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
1997, Texas Instruments Incorporated
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
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