参数资料
型号: SN74LS112AD
厂商: MOTOROLA INC
元件分类: 锁存器
英文描述: LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
封装: SOIC-16
文件页数: 1/2页
文件大小: 47K
代理商: SN74LS112AD
5-1
FAST AND LS TTL DATA
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and
asynchronous set and clear inputs to each flip-flop. When the clock goes
HIGH, the inputs are enabled and data will be accepted. The logic level of the
J and K inputs may be allowed to change when the clock pulse is HIGH and
the bistable will perform according to the truth table as long as minimum set-up
and hold time are observed. Input data is transferred to the outputs on the
negative-going edge of the clock pulse.
LOGIC DIAGRAM (Each Flip-Flop)
Q
5(9)
CLEAR (CD)
15(14)
J
3(11)
Q
6(7)
SET (SD)
4(10)
K
2(12)
1(13)
CLOCK (CP)
MODE SELECT — TRUTH TABLE
OPERATING MODE
INPUTS
OUTPUTS
OPERATING MODE
SD
CD
J
K
Q
Set
Reset (Clear)
*Undetermined
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
L
H
L
H
L
H
X
h
l
h
l
X
h
l
H
L
H
q
L
H
q
L
H
q
H
L
q
* Both outputs will be HIGH while both SD and CD are LOW, but the output states
are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the HIGH to LOW clock transition.
SN54/74LS112A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN
Plastic
SN74LSXXXD
SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03
LOGIC SYMBOL
VCC = PIN 16
GND = PIN 8
4
3
1
2
15
5
6
SD
J
CP
K CD Q
Q
10
11
9
13
12
14
7
SD
J
CP
K CD Q
Q
相关PDF资料
PDF描述
SN54LS113AJ LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14
SN54LS114AJD LS SERIES, NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14
SN54LS125AJD LS SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, CDIP14
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相关代理商/技术参数
参数描述
SN74LS112ADE4 功能描述:触发器 Dual Neg-Edge-Trig J-K Flip-Flop RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel
SN74LS112ADG4 功能描述:触发器 Dual J to K Neg Edge Trigrd FlipFlop RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel
SN74LS112ADR 功能描述:触发器 Dual Neg-Edge-Trig J-K Flip-Flop RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel
SN74LS112ADRE4 功能描述:触发器 Dual Neg-Edge-Trig J-K Flip-Flop RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel
SN74LS112ADRG4 功能描述:触发器 Dual J to K Neg Edge Trigrd FlipFlop RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel