参数资料
型号: SN74LS157MEL
厂商: ON SEMICONDUCTOR
元件分类: 编、解码器及复用、解复用
英文描述: LS SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16
封装: EIAJ, SO-16
文件页数: 3/7页
文件大小: 173K
代理商: SN74LS157MEL
SN74LS157
http://onsemi.com
3
Figure 3. Logic Diagram
14
1
26
7
3
4
5
9
11
12
10
13
15
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
FUNCTIONAL DESCRIPTION
The LS157 is a Quad 2-Input Multiplexer fabricated with
the Schottky barrier diode process for high speed. It selects
four bits of data from two sources under the control of a
common Select Input (S). The Enable Input (E) is active
LOW. When E is HIGH, all of the outputs (Z) are forced
LOW regardless of all other inputs.
The LS157 is the logic implementation of a 4-pole,
2-position switch where the position of the switch is
determined by the logic levels supplied to the Select Input.
The logic equations for the outputs are:
Za = E (I1a S + I0a S)
Zb = E (I1b S + I0b S)
Zc = E (I1c S + I0c S)Zd = E (I1d S + I0d S)
A common use of the LS157 is the moving of data from
two groups of registers to four common output busses. The
particular register from which the data comes is determined
by the state of the Select Input. A less obvious use is as a
function generator. The LS157 can generate any four of
the 16 different functions of two variables with one variable
common. This is useful for implementing highly irregular
logic.
TRUTH TABLE
ENABLE
SELECT
INPUT
INPUTS
OUTPUT
E
S
I0
I1
Z
H
X
L
H
X
LL
L
H
X
HH
L
XL
L
H
X
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
相关PDF资料
PDF描述
SN74LS157ND LS SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDIP16
SN74LS15JDS LS SERIES, TRIPLE 3-INPUT AND GATE, CDIP14
SN74LS160ADR2 LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO16
SN74LS161AD LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
SN74LS162AD LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO16
相关代理商/技术参数
参数描述
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