参数资料
型号: SN74LS161ADR2
厂商: ON SEMICONDUCTOR
元件分类: 计数器
英文描述: LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
封装: PLASTIC, SOIC-16
文件页数: 6/8页
文件大小: 199K
代理商: SN74LS161ADR2
SN74LS161A, SN74LS163A
http://onsemi.com
6
Figure 3.
The positive TC pulse occurs when the outputs are in the (Q0
Q1 Q2 Q3) state for the LS161 and LS163.
OTHER CONDITIONS: CP = PE = CEP = MR = H
1.3 V
tPHL
tPLH
1.3 V
CET
TC
AC WAVEFORMS (continued)
The positive TC pulse is coincident with the output state
(Q0 Q1 Q2 Q3) for the LS161 and LS163.
Figure 4.
OTHER CONDITIONS: PE = CEP = CET = MR = H
1.3 V
tPLH
tPHL
CP
TC
The shaded areas indicate when the input is permitted to
change for predictable output performance.
Figure 5.
1.3 V
OTHER CONDITIONS: PE = L, MR = H
CP
1.3 V
ts(H)
ts(L)
th(H) = 0
th(L) = 0
Q0 w Q1 w Q2 w Q3
P0 w P1 w P2 w P3
OTHER CONDITIONS: PE = H, MR = H
1.3 V
ts(H)
ts(L)
th(H) = 0
th(L) = 0
ts(H)
th(H) = 0
ts(L)
th(L) = 0
COUNT
HOLD
CEP
CP
CET
Q
CP
SR or PE
Q RESPONSE TO PE
RESET
COUNT OR LOAD
Q RESPONSE TO SR
PARALLEL LOAD
(See Fig. 5)
COUNT MODE
(See Fig. 7)
ts(L)
ts(H)
th
(L) = 0
th(H) = 0
1.3 V
Figure 6.
COUNT ENABLE TRICKLE INPUT
TO TERMINAL COUNT OUTPUT DELAYS
CLOCK TO TERMINAL COUNT DELAYS
SETUP TIME (ts) AND HOLD TIME (th)
FOR PARALLEL DATA INPUTS
SETUP TIME (ts) AND HOLD TIME (th) FOR
COUNT ENABLE (CEP) AND (CET) AND
PARALLEL ENABLE (PE) INPUTS
Figure 7.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
1.3 V
相关PDF资料
PDF描述
SN74LS161AN LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16
SMS49S1A2H45A@FREQ5 QUARTZ CRYSTAL RESONATOR, 10 MHz - 13.9 MHz
SMS49O1A2H40E@FREQ QUARTZ CRYSTAL RESONATOR, 3.5 MHz - 40 MHz
SMS49N3C1H40E@FREQ QUARTZ CRYSTAL RESONATOR, 28.1 MHz - 60 MHz
SMS49L1E5H30A@FREQ QUARTZ CRYSTAL RESONATOR, 3.5 MHz - 40 MHz
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