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参数资料
| 型号： | SN74LS165DR2 |
| 厂商： | ON SEMICONDUCTOR |
| 元件分类： | 计数移位寄存器 |
| 英文描述： | LS SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PDSO16 |
| 封装： | PLASTIC, SOIC-16 |
| 文件页数： | 3/8页 |
| 文件大小： | 197K |
| 代理商： | SN74LS165DR2 |
SN74LS165
http://onsemi.com
3
LOGIC DIAGRAM
PL
CP1
P4
P6
P5
P7
CP2
P3
P1
P2
P0
DS
PRESET
S
CP
R CL
Q0
PRESET
S
CP
R CL
Q1
PRESET
S
CP
R CL
Q2
PRESET
S
CP
R CL
Q3
PRESET
S
CP
R CL
Q4
PRESET
S
CP
R CL
Q5
PRESET
S
CP
R CL
Q6
PRESET
S
CP
R CL
Q7
14
1
2
6
3
4
5
11
12
10
13
15
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
7
9
FUNCTIONAL DESCRIPTION
The SN74LS165 contains eight clocked master/slave RS
flip-flops connected as a shift register, with auxiliary gating
to provide overriding asynchronous parallel entry. Parallel
data enters when the PL signal is LOW. The parallel data can
change while PL is LOW, provided that the recommended
setup and hold times are observed.
For clock operation, PL must be HIGH. The two clock
inputs perform identically; one can be used as a clock inhibit
by applying a HIGH signal. To avoid double clocking,
however, the inhibit signal should only go HIGH while the
clock is HIGH. Otherwise, the rising inhibit signal will cause
the same response as a rising clock edge. The flip-flops are
edge-triggered for serial operations. The serial input data
can change at any time, provided only that the recommended
setup and hold times are observed, with respect to the rising
edge of the clock.
TRUTH TABLE
PL
CP
CONTENTS
RESPONSE
1
2
Q0 Q1
Q2
Q3
Q4 Q5
Q6 Q7
L
X
P0
P1
P2
P3
P4
P5
P6
P7
Parallel Entry
H
L
DS Q0
Q1
Q2
Q3 Q4
Q5 Q6
Right Shift
H
Q0 Q1
Q2
Q3
Q4 Q5
Q6 Q7
No Change
H
L
DS Q0
Q1
Q2
Q3 Q4
Q5 Q6
Right Shift
H
Q0 Q1
Q2
Q3
Q4 Q5
Q6 Q7
No Change
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
相关PDF资料 |
PDF描述 |
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| SN74LS166JDS | LS SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16 |
| SN74LS166MEL | LS SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 |
| SN74LS171N | LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 |
| SNJ54LS171J | LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SN74LS165J | 制造商:Motorola Inc 功能描述: |
| SN74LS165MEL | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:ON Semiconductor 功能描述: |
| SN74LS165MR1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:ON Semiconductor 功能描述: |
| SN74LS165N | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN74LS166AD | 功能描述:计数器移位寄存器 Serial-out shift Registers RoHS:否 制造商:Texas Instruments 计数器类型: 计数顺序:Serial to Serial/Parallel 电路数量:1 封装 / 箱体:SOIC-20 Wide 逻辑系列: 逻辑类型: 输入线路数量:1 输出类型:Open Drain 传播延迟时间:650 ns 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装:Reel |
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