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参数资料
| 型号： | SN74LS173ANSR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 锁存器 |
| 英文描述： | LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16 |
| 封装： | GREEN, PLASTIC, SOP-16 |
| 文件页数： | 1/20页 |
| 文件大小： | 643K |
| 代理商： | SN74LS173ANSR |
SN54173, SN54LS173A, SN74173, SN74LS173A
4-BIT D-TYPE REGISTERS
WITH 3-STATE OUTPUTS
SDLS067A – OCTOBER 1976 – REVISED JUNE 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D 3-State Outputs Interface Directly With
System Bus
D Gated Output-Control LInes for Enabling or
Disabling the Outputs
D Fully Independent Clock Virtually
Eliminates Restrictions for Operating in
One of Two Modes:
– Parallel Load
– Do Nothing (Hold)
D For Application as Bus Buffer Registers
D Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Flat
(W) Packages, Ceramic Chip Carriers (FK),
and Standard Plastic (N) and Ceramic (J)
DIPs
TYPE
TYPICAL
PROPAGATION
DELAY TIME
MAXIMUM
CLOCK
FREQUENCY
’173
23 ns
35 MHz
’LS173A
18 ns
50 MHz
description
The ’173 and ’LS173A 4-bit registers include
D-type flip-flops featuring totem-pole 3-state
outputs capable of driving highly capacitive
or
relatively
low-impedance
loads.
The
high-impedance
third
state
and
increased
high-logic-level drive provide these flip-flops with
the capability of being connected directly to and
driving the bus lines in a bus-organized system without need for interface or pull-up components. Up to 128 of
the SN74173 or SN74LS173A outputs can be connected to a common bus and still drive two Series 54/74 or
54LS/74LS TTL normalized loads, respectively. Similarly, up to 49 of the SN54173 or SN54LS173A outputs can
be connected to a common bus and drive one additional Series 54/74 or 54LS/74LS TTL normalized load,
respectively. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic
levels, the output control circuitry is designed so that the average output disable times are shorter than the
average output enable times.
Gated enable inputs are provided on these devices for controlling the entry of data into the flip-flops. When both
data-enable (G1, G2) inputs are low, data at the D inputs are loaded into their respective flip-flops on the next
positive transition of the buffered clock input. Gate output-control (M, N) inputs also are provided. When both
are low, the normal logic states (high or low levels) of the four outputs are available for driving the loads or bus
lines. The outputs are disabled independently from the level of the clock by a high logic level at either
output-control input. The outputs then present a high impedance and neither load nor drive the bus line. Detailed
operation is given in the function table.
The SN54173 and SN54LS173A are characterized for operation over the full military temperature range of
–55
°C to 125°C. The SN74173 and SN74LS173A are characterized for operation from 0°C to 70°C.
Copyright
1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
M
N
1Q
2Q
3Q
4Q
CLK
GND
VCC
CLR
1D
2D
3D
4D
G2
G1
SN54173, SN54LS173A ...J OR W PACKAGE
SN74173 ...N PACKAGE
SN74LS173A ...D or N PACKAGE
(TOP VIEW)
32
1 20 19
910 11 12 13
4
5
6
7
8
18
17
16
15
14
1D
2D
NC
3D
4D
1Q
2Q
NC
3Q
4Q
SN54LS173A . . . FK PACKAGE
(TOP VIEW)
N
M
NC
CLR
GND
NC
CC
V
NC – No internal connection
G2
G1
CLK
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
相关PDF资料 |
PDF描述 |
|---|---|
| SN74LS175NS | LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| SN74LS17DR | LS SERIES, HEX 1-INPUT NON-INVERT GATE, PDSO14 |
| SN74LS07DR | LS SERIES, HEX 1-INPUT NON-INVERT GATE, PDSO14 |
| SN74LS192FN | LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, PQCC20 |
| SN54L192J | TTL/H/L SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, CDIP16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SN74LS173ANSRE4 | 功能描述:触发器 4-Bit D-type Reg With 3-State Outputs RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel |
| SN74LS173ANSRG4 | 功能描述:触发器 4B D Type Registers RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel |
| SN74LS173N TI84 | 制造商:TI 功能描述:74LS173N |
| SN74LS173NTI84 | 制造商:TI 功能描述:74LS173N |
| SN74LS174 | 制造商:Motorola Inc 功能描述: |
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