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参数资料
| 型号： | SN74LS175DR2 |
| 厂商： | ON SEMICONDUCTOR |
| 元件分类： | 锁存器 |
| 英文描述： | LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 封装： | PLASTIC, SOIC-16 |
| 文件页数： | 4/7页 |
| 文件大小： | 179K |
| 代理商： | SN74LS175DR2 |
SN74LS175
http://onsemi.com
4
AC CHARACTERISTICS (TA = 25°C)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
fMAX
Maximum Input Clock Frequency
30
40
MHz
VCC = 5.0 V
CL = 15 pF
tPLH
tPHL
Propagation Delay, MR to Output
20
30
ns
tPLH
tPHL
Propagation Delay, Clock to Output
13
16
25
ns
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
Parameter
Limits
Unit
Test Conditions
Min
Typ
Max
tW
Clock or MR Pulse Width
20
ns
VCC = 5.0 V
ts
Data Setup Time
20
ns
th
Data Hold Time
5.0
ns
trec
Recovery Time
25
ns
AC WAVEFORMS
Figure 1. Clock to Output Delays, Clock Pulse Width,
Frequency, Setup and Hold Times Data to Clock
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
1.3 V
Q
tPLH
tPHL
1.3 V
*The shaded areas indicate when the input is permitted to
*change for predictable output performance.
1.3 V
1/fmax
tw
ts(H)
th(H)
ts(L)
th(L)
CP
tPHL
tPLH
tW
tPHL
CP
trec
Q
MR
D
Q
*
1.3 V
DEFINITIONS OF TERMS
SETUP TIME (ts) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW to HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time
following the clock transition from LOW to HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW to HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
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PDF描述 |
|---|---|
| SN74LS175NS | LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 |
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| SN74LS182NS | LS SERIES, 4-BIT LOOK-AHEAD CARRY GENERATOR, PDIP16 |
| SN74LS183NDS | LS SERIES, 1-BIT ADDER/SUBTRACTOR, PDIP14 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SN74LS175DRE4 | 功能描述:触发器 Quadruple D-Type Flip-Flop W/Clear RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel |
| SN74LS175DRG4 | 功能描述:触发器 Quad D Type FlipFlop RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel |
| SN74LS175J | 制造商:Motorola Inc 功能描述: |
| SN74LS175M | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN74LS175N | 功能描述:触发器 Quad RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel |
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