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参数资料
| 型号： | SN74LS194ADR2 |
| 厂商： | ON SEMICONDUCTOR |
| 元件分类： | 计数移位寄存器 |
| 英文描述： | LS SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 |
| 封装： | PLASTIC, SOIC-16 |
| 文件页数： | 3/7页 |
| 文件大小： | 182K |
| 代理商： | SN74LS194ADR2 |
SN74LS194A
http://onsemi.com
3
LOGIC DIAGRAM
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
S1
S0
DSR
DSL
CP
MR
Q0
Q1
Q2
Q3
P0
P1
P2
P3
14
1
2
6
7
3
4
5
9
11
12
10
13
15
SQ0
CP
R
CLEAR
SQ1
CP
R
CLEAR
SQ2
CP
R
CLEAR
SQ3
CP
R
CLEAR
FUNCTIONAL DESCRIPTION
The Logic Diagram and Truth Table indicate the
functional characteristics of the LS194A 4-Bit Bidirectional
Shift Register. The LS194A is similar in operation to the
ON Semiconductor LS195A Universal Shift Register when
used in serial or parallel data register transfers. Some of the
common features of the two devices are described below:
All data and mode control inputs are edge-triggered,
responding only to the LOW to HIGH transition of the Clock
(CP). The only timing restriction, therefore, is that the mode
control and selected data inputs must be stable one set-up
time prior to the positive transition of the clock pulse.
The register is fully synchronous, with all operations
taking place in less than 15 ns (typical) making the device
especially useful for implementing very high speed CPUs,
or the memory buffer registers.
The four parallel data inputs (P0, P1, P2, P3) are D-type
inputs. When both S0 and S1 are HIGH, the data appearing
on P0, P1, P2, and P3 inputs is transferred to the Q0, Q1, Q2,
and Q3 outputs respectively following the next LOW to
HIGH transition of the clock.
The asynchronous Master Reset (MR), when LOW,
overrides all other input conditions and forces the Q outputs
LOW.
Special logic features of the LS194A design which
increase the range of application are described below:
Two mode control inputs (S0, S1) determine the
synchronous operation of the device. As shown in the Mode
Selection Table, data can be entered and shifted from left to
right (shift right, Q0 ! Q1, etc.) or right to left (shift left, Q3
! Q2, etc.), or parallel data can be entered loading all four
bits of the register simultaneously. When both S0 and S1,are
LOW, the existing data is retained in a “do nothing” mode
without restricting the HIGH to LOW clock transition.
D-type serial data inputs (DSR, DSL) are provided on both
the first and last stages to allow multistage shift right or shift
left data transfers without interfering with parallel load
operation.
相关PDF资料 |
PDF描述 |
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| SN74LS194AND | LS SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16 |
| SN74LS194AJD | LS SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16 |
| SN74LS195AJD | LS SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16 |
| SN74LS195N-00 | LS SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16 |
| SNJ54195W-10 | TTL/H/L SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SN74LS194ADRE4 | 功能描述:计数器移位寄存器 Bi-dir universal Shift Register RoHS:否 制造商:Texas Instruments 计数器类型: 计数顺序:Serial to Serial/Parallel 电路数量:1 封装 / 箱体:SOIC-20 Wide 逻辑系列: 逻辑类型: 输入线路数量:1 输出类型:Open Drain 传播延迟时间:650 ns 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装:Reel |
| SN74LS194ADRG4 | 功能描述:计数器移位寄存器 Bidirectnal Univrsal Shift Registers RoHS:否 制造商:Texas Instruments 计数器类型: 计数顺序:Serial to Serial/Parallel 电路数量:1 封装 / 箱体:SOIC-20 Wide 逻辑系列: 逻辑类型: 输入线路数量:1 输出类型:Open Drain 传播延迟时间:650 ns 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装:Reel |
| SN74LS194AJ | 制造商:Motorola Inc 功能描述: |
| SN74LS194AN | 功能描述:计数器移位寄存器 Bi-dir universal Shift Register RoHS:否 制造商:Texas Instruments 计数器类型: 计数顺序:Serial to Serial/Parallel 电路数量:1 封装 / 箱体:SOIC-20 Wide 逻辑系列: 逻辑类型: 输入线路数量:1 输出类型:Open Drain 传播延迟时间:650 ns 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装:Reel |
| SN74LS194AN3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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