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参数资料
| 型号： | SN74LS259MEL |
| 厂商： | ON SEMICONDUCTOR |
| 元件分类： | 锁存器 |
| 英文描述： | LS SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDSO16 |
| 封装： | EIAJ, SOP-16 |
| 文件页数： | 3/8页 |
| 文件大小： | 237K |
| 代理商： | SN74LS259MEL |
E
C
MODE
L
H
L
H
L
Addressable Latch
Memory
Active HIGH Eight-Channel
Demultiplexer
Clear
MODE SELECTION
X = Don’t Care Condition
L = LOW Voltage Level
H = HIGH Voltage Level
QN1 = Previous Output State
SN74LS259
http://onsemi.com
3
LOGIC DIAGRAM
E
DA0
A1
A2
C
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
14
12
67
3
4
5
9
11
12
10
13
15
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
FUNCTIONAL DESCRIPTION
The SN74LS259 has four modes of operation as shown in
the mode selection table. In the addressable latch mode, data
on the Data line (D) is written into the addressed latch.The
addressed latch will follow the data input with all
non-addressed latches remaining in their previous states. In
the memory mode, all latches remain in their previous state
and are unaffected by the Data or Address inputs.
In the one-of-eight decoding or demultiplexing mode, the
addressed output will follow the state of the D input with all
other inputs in the LOW state. In the clear mode all outputs
are LOW and unaffected by the address and data inputs.
When operating the SN74LS259 as an addressable latch,
changing more then one bit of the address could impose a
transient wrong address. Therefore, this should only be done
while in the memory mode.
The truth table below summarizes the operations.
TRUTH TABLE
PRESENT OUTPUT STATES
C E D A0 A1 A2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
MODE
L H X X
X
L
Clear
L LL L
L
Demultiplex
L LH L
L
H
LL
L
L LL H
L
LL
L
L LH H
L
HL
L
L LH H
H
L
LL
L
H
H H X X
X
QN1
Memory
H I I
L
QN1
Addressable
H LH L
L
H
QN1
Latch
H LL H
L
QN1
LQN1
H LH H
L
QN1
HQN1
H LL H
H
QN1
L
H L H H
H
QN1
H
相关PDF资料 |
PDF描述 |
|---|---|
| SN74LS259ND | LS SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP16 |
| SN54LS259JD | LS SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, CDIP16 |
| SN74LS260J | LS SERIES, DUAL 5-INPUT NOR GATE, CDIP14 |
| SN74LS260ND | LS SERIES, DUAL 5-INPUT NOR GATE, PDIP14 |
| SN74LS260NDS | LS SERIES, DUAL 5-INPUT NOR GATE, PDIP14 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SN74LS259ND | 制造商:TI 功能描述:74LS259 S10L1B |
| SN74LS2600D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN74LS260N | 制造商:Motorola 功能描述:74LS260 MOT'93 |
| SN74LS261D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN74LS266D | 功能描述:逻辑门 Quad 2 Input RoHS:否 制造商:Texas Instruments 产品:OR 逻辑系列:LVC 栅极数量:2 线路数量（输入/输出）:2 / 1 高电平输出电流:- 16 mA 低电平输出电流:16 mA 传播延迟时间:3.8 ns 电源电压-最大:5.5 V 电源电压-最小:1.65 V 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:DCU-8 封装:Reel |
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