- 您现在的位置：买卖IC网 > PDF目录98120 > SN74LV166APWT (TEXAS INSTRUMENTS INC) LV/LV-A/LVX/H SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 PDF资料下载
参数资料
| 型号： | SN74LV166APWT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 计数移位寄存器 |
| 英文描述： | LV/LV-A/LVX/H SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 |
| 封装： | GREEN, PLASTIC, TSSOP-16 |
| 文件页数： | 12/19页 |
| 文件大小： | 588K |
| 代理商： | SN74LV166APWT |
SN54LV166A, SN74LV166A
8BIT PARALLELLOAD SHIFT REGISTERS
SCLS456C FEBRUARY 2001 REVISED APRIL 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
The ’LV166A parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an
overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift / load (SH/LD) input.
When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each
clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs
on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the
low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a
clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low
enables the other clock input. This allows the system clock to be free running, and the register can be stopped
on command with the other clock input. CLK INH should be changed to the high level only when CLK is high.
CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS
OUTPUTS
INPUTS
INTERNAL
CLR
SH/LD
CLK INH
CLK
SER
PARALLEL
A...H
QA
QB
QH
L
X
L
H
XL
L
X
QA0
QB0
QH0
H
LL
↑
X
a ...h
a
bh
H
HL
↑
HX
H
QAn
QGn
H
HL
↑
LX
L
QAn
QGn
H
X
H
↑
X
QA0
QB0
QH0
相关PDF资料 |
PDF描述 |
|---|---|
| SN74LV166APWTE4 | LV/LV-A/LVX/H SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 |
| SN74LV174ADBR | LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16 |
| SN74LV174ADE4 | LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16 |
| SN74LV174AD | LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16 |
| SN74LV174APWE4 | LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SN74LV166APWTE4 | 功能描述:计数器移位寄存器 8-Bit Parallel-Load Shift Register RoHS:否 制造商:Texas Instruments 计数器类型: 计数顺序:Serial to Serial/Parallel 电路数量:1 封装 / 箱体:SOIC-20 Wide 逻辑系列: 逻辑类型: 输入线路数量:1 输出类型:Open Drain 传播延迟时间:650 ns 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装:Reel |
| SN74LV166APWTG4 | 功能描述:计数器移位寄存器 Parallel Load 8B Shift Registers RoHS:否 制造商:Texas Instruments 计数器类型: 计数顺序:Serial to Serial/Parallel 电路数量:1 封装 / 箱体:SOIC-20 Wide 逻辑系列: 逻辑类型: 输入线路数量:1 输出类型:Open Drain 传播延迟时间:650 ns 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装:Reel |
| SN74LV174AD | 功能描述:触发器 Hex w/ Clear RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel |
| SN74LV174ADBR | 功能描述:触发器 Hex D-Type Flip-Flop With Clear RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel |
| SN74LV174ADBRE4 | 功能描述:触发器 Hex D-Type Flip-Flop With Clear RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。