参数资料
型号: SN74LV221ADBLE
厂商: TEXAS INSTRUMENTS INC
元件分类: 谐振器
英文描述: LV/LV-A/LVX/H SERIES, DUAL MONOSTABLE MULTIVIBRATOR, PDSO16
封装: SSOP-16
文件页数: 1/13页
文件大小: 213K
代理商: SN74LV221ADBLE
SN54LV221A, SN74LV221A
DUAL MONOSTABLE MULTIVIBRATORS
WITH SCHMITT-TRIGGER INPUTS
SCLS450B – DECEMBER 1999 – REVISED AUGUST 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D EPIC (Enhanced-Performance Implanted
CMOS) Process
D 2-V to 5.5-V VCC Operation
D Support Mixed-Mode Voltage Operation on
All Ports
D Schmitt-Trigger Circuitry on A, B, and CLR
Inputs for Slow Input Transition Rates
D Edge Triggered From Active-High or
Active-Low Gated Logic Inputs
D Overriding Clear Terminates Output Pulse
D Glitch-Free Power-Up Reset on Outputs
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)
description
The ’LV221A devices are dual multivibrators
designed for 2-V to 5.5-V VCC operation. Each
multivibrator has a negative-transition-triggered
(A) input and a positive-transition-triggered (B)
input, either of which can be used as an inhibit
input.
These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method,
the A input is low and the B input goes high. In the second method, the B input is high and the A input goes low.
In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.
The output pulse duration is programmable by selecting external resistance and capacitance values. The
external timing capacitor must be connected between Cext and Rext/Cext(positive) and an external resistor
connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistor
between Rext/Cext and VCC. The output pulse duration can also be reduced by taking CLR low.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition
rates with jitter-free triggering at the outputs.
Copyright
2000, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LV221A ...J OR W PACKAGE
SN74LV221A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
SN54LV221A . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1A
1B
1CLR
1Q
2Q
2Cext
2Rext/Cext
GND
VCC
1Rext/Cext
1Cext
1Q
2Q
2CLR
2B
2A
32
1 20 19
910 11 1213
4
5
6
7
8
18
17
16
15
14
1Cext
1Q
NC
2Q
2CLR
1CLR
1Q
NC
2Q
2Cext
1B
1A
NC
2A
2B
V
1R
2R
GND
NC
CC
NC – No internal connection
ext
/C
ext
/C
ext
DESIGN GOAL information is current as of publication date. Products are
experimental, developmental, or prototype, and product specifications
are subject to change without notice. TI makes no warranty as to these
products and does not represent that a final production version will be
sold by TI.
EPIC is a trademark of Texas Instruments.
相关PDF资料
PDF描述
SN54LV245AW LV/LV-A/LVX/H SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, CDFP20
SN74LV245ANS LV/LV-A/LVX/H SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20
SN54LV245AFK LV/LV-A/LVX/H SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, CQCC20
SN54LV245AJ LV/LV-A/LVX/H SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, CDIP20
SN54LV273AJ LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP20
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