参数资料
型号: SN74LVC241A
厂商: Texas Instruments, Inc.
英文描述: Octal Buffer/Driver With 3-State Outputs(带有三态输出的八路缓冲器/驱动器)
中文描述: 八路缓冲器/驱动器与三态输出(带有三态输出的八路缓冲器/驱动器)
文件页数: 1/5页
文件大小: 93K
代理商: SN74LVC241A
SN74LVC241A
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS343C – MARCH 1994 – REVISED JANUARY 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Typical V
OHV
(Output V
OH
Undershoot)
> 2 V at V
CC
= 3.3 V, T
A
= 25
°
C
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V V
CC
)
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages
description
This octal buffer/line driver is designed for 2.7-V to 3.6-V V
CC
operation.
The SN74LVC241A is designed specifically to improve both the performance and density of 3-state
memory-address drivers, clock drivers, and bus-oriented receivers and transmitters. Together with the
’LVC240A and ’LVC244A, these devices provide the choice of selected combinations of inverting and
noninverting outputs, symmetrical OE (active-low output-enable) inputs, and complementary OE and
OE inputs.
The SN74LVC241A is organized as two 4-bit line drivers with separate output-enable (1OE, 2OE) inputs. When
1OE is low or 2OE is high, the device passes data from the A inputs to the Y outputs. When 1OE is high or 2OE
is low, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sinking or the current-sourcing capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
The SN74LVC241A is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLES
INPUTS
1OE
OUTPUT
1Y
1A
L
H
H
L
L
L
H
X
Z
INPUTS
OUTPUT
2Y
2OE
2A
H
H
H
H
L
L
L
X
Z
Copyright
1997, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
V
CC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
DB, DW, OR PW PACKAGE
(TOP VIEW)
P
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