参数资料
型号: SN74LVC2G14YZPR
厂商: TEXAS INSTRUMENTS INC
元件分类: 门电路
英文描述: LVC/LCX/Z SERIES, DUAL 1-INPUT INVERT GATE, BGA6
封装: GREEN, DSBGA-6
文件页数: 1/16页
文件大小: 615K
代理商: SN74LVC2G14YZPR
www.ti.com
FEATURES
3
2
4
6
1
1A
1Y
2Y
GND
2A
DBV PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
DCK PACKAGE
(TOP VIEW)
3
2
4
6
1
1A
1Y
2Y
GND
2A
1A
2A
1Y
2Y
GND
See mechanical drawings for dimensions.
1
4
2
3
6
VCC
5
VCC
5
DESCRIPTION/ORDERING INFORMATION
DUAL SCHMITT-TRIGGER INVERTER
SCES200L – APRIL 1999 – REVISED JANUARY 2007
Available in the Texas Instruments
Typical V
OHV (Output VOH Undershoot)
NanoFree Package
>2 V at V
CC = 3.3 V, TA = 25°C
Supports 5-V V
CC Operation
I
off Feature Supports Partial-Power-Down
Mode Operation
Inputs Accept Voltages to 5.5 V
Latch-Up Performance Exceeds 100 mA Per
Max t
pd of 5.4 ns at 3.3 V
JESD 78, Class II
Low Power Consumption, 10-A Max I
CC
ESD Protection Exceeds JESD 22
±24-mA Output Drive at 3.3 V
2000-V Human-Body Model (A114-A)
Typical V
OLP (Output Ground Bounce)
1000-V Charged-Device Model (C101)
<0.8 V at V
CC = 3.3 V, TA = 25°C
This dual Schmitt-trigger inverter is designed for 1.65-V to 5.5-V VCC operation.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
The SN74LVC2G14 contains two inverters and performs the Boolean function Y = A. The device functions as
two independent inverters, but because of Schmitt action, it may have different input threshold levels for
positive-going (VT+) and negative-going (VT–) signals.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(2)
NanoFree – WCSP (DSBGA)
Reel of 3000
SN74LVC2G14YZPR
_ _ _CF_
0.23-mm Large Bump – YZP (Pb-free)
Reel of 3000
SN74LVC2G14DBVR
SOT (SOT-23) – DBV
C14_
–40°C to 85°C
Reel of 250
SN74LVC2G14DBVT
Reel of 3000
SN74LVC2G14DCKR
SOT (SC-70) – DCK
CF_
Reel of 250
SN74LVC2G14DCKT
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2)
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
= Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 1999–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
相关PDF资料
PDF描述
SN74LVC2G157DCUR LV/LV-A/LVX/H SERIES, 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO8
SN74LVC2G157YEPR LVC/LCX/Z SERIES, 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PBGA8
SN74LVC2G17YEAR LVC/LCX/Z SERIES, DUAL 1-INPUT NON-INVERT GATE, BGA6
SN74LVC2G17YEPR LVC/LCX/Z SERIES, DUAL 1-INPUT NON-INVERT GATE, BGA6
SN74LVC2G240YZAR LVC/LCX/Z SERIES, DUAL 1-BIT DRIVER, INVERTED OUTPUT, PBGA8
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