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| 型号： | SN74LVC543PW |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS |
| 中文描述： | 登记收发器八路三态输出 |
| 文件页数： | 1/6页 |
| 文件大小： | 99K |
| 代理商： | SN74LVC543PW |
SN74LVC543
OCTAL REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS299A – JANUARY 1993 – REVISED JULY 1995
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Typical V
OHV
(Output V
OH
Undershoot)
> 2 V at V
CC
= 3.3 V, T
A
= 25
°
C
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages
description
This octal registered transceiver is designed for
2.7-V to 3.6-V V
CC
operation.
The SN74LVC543 contains two sets of D-type latches for temporary storage of data flowing in either direction.
Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each
register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and
LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB places the A
latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the
data present at the output of the A latches. Data flow for B to A is similar to that of A to B but uses CEBA, LEBA,
and OEBA.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVC543 is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE
INPUTS
OUTPUT
B
CEAB
H
LEAB
X
OEAB
X
A
X
Z
X
X
H
X
Z
L
H
L
X
B0
L
L
L
L
L
L
L
L
H
H
A-to-B data flow is shown; B-to-A flow control is the
same except that it uses CEBA, LEBA, and OEBA.
Output level before the indicated steady-state input
conditions were established
Copyright
1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DB, DW, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
LEBA
OEBA
A1
A2
A3
A4
A5
A6
A7
A8
CEAB
GND
V
CC
CEBA
B1
B2
B3
B4
B5
B6
B7
B8
LEAB
OEAB
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| SN74LVC573ADBR | 功能描述:闭锁 Tri-St Octal D-Type RoHS:否 制造商:Micrel 电路数量:1 逻辑类型:CMOS 逻辑系列:TTL 极性:Non-Inverting 输出线路数量:9 高电平输出电流: 低电平输出电流: 传播延迟时间: 电源电压-最大:12 V 电源电压-最小:5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-16 封装:Reel |
| SN74LVC573ADBRE4 | 功能描述:闭锁 Tri-St Octal D-Type RoHS:否 制造商:Micrel 电路数量:1 逻辑类型:CMOS 逻辑系列:TTL 极性:Non-Inverting 输出线路数量:9 高电平输出电流: 低电平输出电流: 传播延迟时间: 电源电压-最大:12 V 电源电压-最小:5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-16 封装:Reel |
| SN74LVC573ADBRG4 | 功能描述:闭锁 Octal Transp DType Latch RoHS:否 制造商:Micrel 电路数量:1 逻辑类型:CMOS 逻辑系列:TTL 极性:Non-Inverting 输出线路数量:9 高电平输出电流: 低电平输出电流: 传播延迟时间: 电源电压-最大:12 V 电源电压-最小:5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-16 封装:Reel |
| SN74LVC573ADGVR | 功能描述:闭锁 Tri-St Octal D-Type RoHS:否 制造商:Micrel 电路数量:1 逻辑类型:CMOS 逻辑系列:TTL 极性:Non-Inverting 输出线路数量:9 高电平输出电流: 低电平输出电流: 传播延迟时间: 电源电压-最大:12 V 电源电压-最小:5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-16 封装:Reel |
| SN74LVC573ADGVRE4 | 功能描述:闭锁 Tri-St Octal D-Type RoHS:否 制造商:Micrel 电路数量:1 逻辑类型:CMOS 逻辑系列:TTL 极性:Non-Inverting 输出线路数量:9 高电平输出电流: 低电平输出电流: 传播延迟时间: 电源电压-最大:12 V 电源电压-最小:5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-16 封装:Reel |
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