参数资料
型号: SN74LVC574AQDWREP
厂商: TEXAS INSTRUMENTS INC
元件分类: 总线收发器
英文描述: LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20
封装: GREEN, PLASTIC, SOIC-20
文件页数: 1/9页
文件大小: 247K
代理商: SN74LVC574AQDWREP
www.ti.com
FEATURES
DW OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
DESCRIPTION/ORDERING INFORMATION
SN74LVC574A-EP
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS750A – DECEMBER 2003 – REVISED AUGUST 2005
Controlled Baseline
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With 3.3-V
– One Assembly/Test Site, One Fabrication
VCC)
Site
Ioff Supports Partial-Power-Down Mode
Extended Temperature Performance of –40
°C
Operation
to 125
°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
Operates From 2 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t
pd of 7 ns at 3.3 V
Typical V
OLP (Output Ground Bounce) <0.8 V
at V
CC = 3.3 V, TA = 25°C
Typical V
OHV (Output VOH Undershoot) >2 V at
V
CC = 3.3 V, TA = 25°C
(1)
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
The SN74LVC574A-EP octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation.
This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance
loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working
registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
SOIC – DW
Reel of 2000
SN74LVC574AQDWREP
C574AEP
–40
°C to 125°C
TSSOP – PW
Reel of 2000
SN74LVC574AQPWREP
C574AEP
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 2003–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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