参数资料
型号: SN74LVT125QDREP
厂商: TEXAS INSTRUMENTS INC
元件分类: 总线收发器
英文描述: LVT SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14
封装: SOIC-14
文件页数: 1/11页
文件大小: 311K
代理商: SN74LVT125QDREP
www.ti.com
FEATURES
D OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
VCC
4OE
4A
4Y
3OE
3A
3Y
DESCRIPTION/ORDERING INFORMATION
SN74LVT125-EP
3.3-V ABT QUADRUPLE BUS BUFFER
WITH 3-STATE OUTPUTS
SCBS796A – JANUARY 2004 – REVISED JUNE 2005
Supports Unregulated Battery Operation
Down to 2.7 V
Controlled Baseline
Typical VOLP (Output Ground Bounce) < 0.8 V
– One Assembly/Test Site, One Fabrication
at VCC = 3.3 V, TA = 25°C
Site
Ioff Supports Partial-Power-Down Mode
Extended Temperature Performance of
Operation
–40
°C to 125°C
Bus-Hold Data Inputs Eliminate the Need for
Enhanced Diminishing Manufacturing
External Pullup Resistors
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree(1)
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Supports Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)
(1)
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
This bus buffer is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a
TTL interface to a 5-V system environment.
The SN74LVT125 features independent line drivers with 3-state outputs. Each output is in the high-impedance
state when the associated output-enable (OE) input is high.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
SOIC – D
Tape and reel
SN74LVT125QDREP
LVT125E
–40
°C to 125°C
TSSOP – PW
Tape and reel
SN74LVT125QPWREP
LVT125E
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 2004–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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