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参数资料
| 型号： | SN74V263-15GGM |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| 中文描述： | 8192】18，16384】18，32768】18，65536】18的3.3V的CMOS先入先出存储器 |
| 文件页数： | 18/52页 |
| 文件大小： | 762K |
| 代理商： | SN74V263-15GGM |
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SN74V263, SN74V273, SN74V283, SN74V293
8192
×
18, 16384
×
18, 32768
×
18, 65536
×
18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D
–
JUNE 2001
–
REVISED FEBRUARY 2003
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional description
timing modes: FWFT mode vs standard mode
The SN74V263, SN74V273, SN74V283, and SN74V293 support two different timing modes of operation:
FWFT or standard. The selection of the mode is determined during master reset by the state of FWFT/SI.
If, at the time of master reset, FWFT/SI is high, then FWFT mode is selected. This mode uses OR to indicate
whether there is valid data at the data outputs (Qn). It also uses IR to indicate whether the FIFO has any free
space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to Qn after three RCLK
rising edges; REN = low is not necessary. Subsequent words must be accessed using REN and RCLK.
If, at the time of master reset, FWFT/SI is low, then standard mode is selected. This mode uses EF to indicate
whether there are any words present in the FIFO. It also uses the FF function to indicate whether the FIFO has
any free space for writing. In standard mode, every word read from the FIFO, including the first, must be
requested, using REN and RCLK.
Various signals (both input and output) operate differently, depending on which timing mode is in effect.
FWFT mode
In FWFT mode, status flags IR, PAF, HF, PAE, and OR operate as outlined in Table 4. To write data into the FIFO,
WEN must be low. Data presented to the DATA IN lines is clocked into the FIFO on subsequent transitions of
WCLK. After the first write is performed, the OR flag goes low after three low-to-high transitions on RCLK.
Subsequent writes continue to fill up the FIFO. PAE goes high after n + 2 words have been loaded into the FIFO,
where n is the empty offset value. The default setting for these values is in the footnote of Table 2. This parameter
also is user programmable (see the
programmable-flag offset loading
section).
If one continues to write data into the FIFO and assumes no read operations are taking place, HF switches to
low after the [(D
–
1)/2 + 2] words were written into the FIFO. If
×
18 input or
×
18 output bus width is selected,
[(D
–
1)/2 + 2] = 4098th word for the SN74V263, 8194th word for SN74V273, 16386th word for the SN74V283,
and 32770th word for the SN74V293. If both
×
9 input and
×
9 output bus widths are selected,
[(D
–
1)/2 + 2] = 8194th word for the SN74V263, 16386th word for SN74V273, 32770th word for the SN74V283,
and 65,538th word for the SN74V293. Continuing to write data into the FIFO causes PAF to go low. Again, if
no reads are performed, the PAF goes low after (D
–
m) writes to the FIFO. If
×
18 input or
×
18 output bus width
is selected, (D
–
m) = (8193
–
m) writes for the SN74V263, (16385
–
m) writes for the SN74V273, (32769
–
m)
writes for the SN74V283, and (65537
–
m) writes for the SN74V293. If both
×
9 input and
×
9 output bus widths
are selected, (D
–
m) = (16385
–
m) writes for the SN74V263, (32769
–
m) writes for the SN74V273, (65537
–
m)
writes for the SN74V283, and (131073
–
m) writes for the SN74V293. The offset m is the full offset value. The
default settings for these values are given in the footnote of Table 2.
When the FIFO is full, the IR flag goes high, inhibiting further write operations. If no reads are performed after
a reset, IR goes high after D writes to the FIFO. If
×
18 input or
×
18 output bus width is selected, D = 8193 writes
for the SN74V263, D = 16385 writes for the SN74V273, D = 32769 writes for the SN74V283, and D = 65537
writes for the SN74V293. If both
×
9 input and
×
9 output bus widths are selected, D = 16385 writes for the
SN74V263, D = 32769 writes for the SN74V273, D = 65537 writes for the SN74V283, and D = 131073 writes
for the SN74V293. Note that the additional word in FWFT mode is due to the capacity of the memory plus output
register.
If the FIFO is full, the first read operation cause the IR flag to go low after two low-to-high transitions of WCLK.
Subsequent read operations causes the PAF and HF to go high at the conditions shown in Table 4. If further
read operations occur without write operations, PAE goes low when there are n + 1 words in the FIFO, where
n is the empty offset value. Continuing read operations causes the FIFO to become empty. When the last word
has been read from the FIFO, OR goes high, inhibiting further read operations. REN is ignored when the FIFO
is empty.
相关PDF资料 |
PDF描述 |
|---|---|
| SN74V263-7GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V273-10GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V273-15GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V273-6GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V273-7GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SN74V263-15PZA | 功能描述:先进先出 8192 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V263-6GGM | 功能描述:先进先出 8192 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V263-6PZA | 功能描述:先进先出 8192 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V263-7GGM | 功能描述:先进先出 8192 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V263-7PZA | 功能描述:先进先出 8192 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
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