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参数资料
| 型号： | SN74V273-10GGM |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| 中文描述： | 8192】18，16384】18，32768】18，65536】18的3.3V的CMOS先入先出存储器 |
| 文件页数： | 9/52页 |
| 文件大小： | 762K |
| 代理商： | SN74V273-10GGM |
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SN74V263, SN74V273, SN74V283, SN74V293
8192
×
18, 16384
×
18, 32768
×
18, 65536
×
18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D
–
JUNE 2001
–
REVISED FEBRUARY 2003
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
partial reset (PRS)
A partial reset is accomplished when the PRS input is taken to a low state. As in the case of the master reset,
the internal read and write pointers are set to the first location of the RAM array, PAE goes low, PAF goes high,
and HF goes high.
Whichever mode is active at the time of partial reset remains selected (FWFT or standard mode). If FWFT mode
is active, OR goes high and IR goes low. If the standard mode is active, FF goes high and EF goes low.
Following partial reset, all values held in the offset registers remain unchanged. The programming method
(parallel or serial) active at the time of partial reset also is retained. The output register is initialized to all zeroes.
PRS is asynchronous.
A partial reset is useful for resetting the device during operation, when reprogramming programmable-flag offset
settings might not be convenient.
See Figure 6 for timing information.
retransmit (RT)
The retransmit operation allows previously read data to be accessed again. There are two modes of retransmit
operation: normal latency and zero latency. There are two stages to retransmit. The first stage is a setup
procedure that resets the read pointer to the first location of memory. The second stage is the actual retransmit,
which consists of reading out the memory contents, starting at the beginning of the memory.
Retransmit setup is initiated by holding RT low during a rising RCLK edge. REN and WEN must be high before
RCLK rises when RT is low. When zero latency is used, REN need not be high before RCLK rises while RT is
low.
If FWFT mode is selected, the FIFO marks the beginning of the retransmit setup by setting OR high. During this
period, the internal read pointer is set to the first location of the RAM array.
When OR goes low, retransmit setup is complete; at the same time, the contents of the first location appear on
the outputs. Because FWFT mode is selected, the first word appears on the outputs and no low on REN is
necessary. Reading all subsequent words requires a low on REN to enable the rising edge of RCLK.
See Figure 12 for timing information.
If standard mode is selected, the FIFO marks the beginning of the retransmit setup by setting EF low. The
change in level is noticeable only if EF was high before setup. During this period, the internal read pointer is
initialized to the first location of the RAM array.
When EF goes high, retransmit setup is complete and read operations can begin, starting with the first location
in memory. Since standard mode is selected, every word read, including the first word following retransmit
setup, requires a low on REN to enable the rising edge of RCLK.
See Figure 11 for timing information.
In retransmit operation, the zero-latency mode can be selected using the retransmit latency mode (RM) pin
during a master reset. This can be applied to the standard mode and the FWFT mode.
retransmit latency mode (RM)
A zero-latency retransmit timing mode can be selected using RM. During master reset, a low on RM selects
zero-latency retransmit. A high on RM during master reset selects normal latency.
If zero-latency retransmit operation is selected, the first data word to be retransmitted is placed on the output
register with respect to the same RCLK edge that initiated the retransmit based on RT being low.
See Figures 13 and 14 for timing information.
相关PDF资料 |
PDF描述 |
|---|---|
| SN74V273-15GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V273-6GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V273-7GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V283-10GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V283-15GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SN74V273-10PZA | 功能描述:先进先出 16384 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V273-15GGM | 功能描述:先进先出 16384 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V273-15PZA | 功能描述:先进先出 16384 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V273-6GGM | 功能描述:先进先出 16384 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V273-6PZA | 功能描述:先进先出 16384 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
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