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| 型号： | SN74V283-6GGM |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| 中文描述： | 8192】18，16384】18，32768】18，65536】18的3.3V的CMOS先入先出存储器 |
| 文件页数： | 7/52页 |
| 文件大小： | 762K |
| 代理商： | SN74V283-6GGM |
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SN74V263, SN74V273, SN74V283, SN74V293
8192
×
18, 16384
×
18, 32768
×
18, 65536
×
18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D
–
JUNE 2001
–
REVISED FEBRUARY 2003
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Table 1. Bus-Matching Configuration Modes
IW
OW
WRITE PORT WIDTH
×
18
×
18
×
9
×
9
READ PORT WIDTH
×
18
×
9
×
18
×
9
L
L
L
H
H
L
H
H
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
BE
I
Big endian/little endian. During master reset, a low on BE selects big-endian operation. A high on BE during master
reset selects little-endian format.
D0
–
D17
I
Data inputs. Data inputs for an 18- or 9-bit bus. When in 18-bit mode, D0
–
D17 are used. When in 9-bit mode, D0
–
D8
are used and the unused inputs (D9
–
D17) should be tied low.
EF/OR
O
Empty flag/output ready. In FWFT mode, the OR function is selected. OR indicates whether there is valid data
available at the outputs. In the standard mode, the EF function is selected. EF indicates whether the FIFO memory
is empty.
FF/IR
O
Full flag/input ready. In FWFT mode, the IR function is selected. IR indicates whether there is space available for
writing to the FIFO memory. In standard mode, the FF function is selected. FF indicates whether the FIFO memory
is full.
FSEL0
I
Flag-select bit 0. During master reset, FSEL0, along with FSEL1 and LD, selects the default offset values for PAE
and PAF. Up to eight possible settings are available.
FSEL1
I
Flag-select bit 1. During master reset, FSEL1, along with FSEL0 and LD, selects the default offset values for PAE
and PAF. Up to eight possible settings are available.
FWFT/SI
I
First-word fall-through/serial in. During master reset, FWFT/SI selects FWFT or standard mode. After master reset,
FWFT/SI functions as a serial input for loading offset registers.
HF
O
Half-full flag. HF indicates whether the FIFO memory is more or less than half full.
IP
I
Interspersed parity. During master reset, a low on IP selects noninterspersed-parity mode. A high on IP selects
interspersed-parity mode.
IW
I
Input width. IW selects the bus width of the write port. During master reset, when IW is low, the write port is configured
with a
×
18 bus width. If IW is high, the write port is a
×
9 bus width.
LD
I
Load. This is a dual-purpose pin. During master reset, the state of the LD input, along with FSEL0 and FSEL1,
determines one of eight default offset values for the PAE and PAF flags, along with the method by which these offset
registers can be programmed, parallel or serial (see Table 2). After master reset, LD enables writing to and reading
from the offset registers.
MRS
I
Master reset. MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During
master reset, the FIFO is configured for either FWFT or standard mode, bus-matching configurations, one of eight
programmable-flag default settings, serial or parallel programming of the offset settings, big-endian/little-endian
format, zero- or normal-latency retransmit, interspersed parity, and synchronous versus asynchronous
programmable-flag timing modes.
OE
I
Output enable. OE controls the output impedance of Qn.
OW
I
Output width. OW selects the bus width of the read port. During master reset, when OW is low, the read port is
configured with a
×
18 bus width. If OW is high, the read port is a
×
9 bus width.
PAE
O
Programmable almost-empty flag. PAE goes low if the number of words in the FIFO memory is less than or equal
to offset n, which is stored in the empty offset register. PAE goes high if the number of words in the FIFO memory
is greater than offset n. Add one if PAE is in FWFT mode.
PAF
O
Programmable almost-full flag. PAF goes high if the number of free locations in the FIFO memory is more than
offset m, which is stored in the full offset register. PAF goes low if the number of free locations in the FIFO memory
is less than or equal to m.
相关PDF资料 |
PDF描述 |
|---|---|
| SN74V283-7GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V293-10GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V293-15GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V293-7GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN75112A | DUAL LINE DRIVERS |
相关代理商/技术参数 |
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| SN74V283-7GGM | 功能描述:先进先出 32768 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V283-7PZA | 功能描述:先进先出 32768 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V283PZAEP | 功能描述:先进先出 Mil Enhance 32768x18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V293-10GGM | 功能描述:先进先出 65536 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
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