SN8P1600
8-bit micro-controller
SONiX TECHNOLOGY CO., LTD
Page 58
Revision 1.94
TC1C COUNTING REGISTER
TC1C is an 8-bit counter register for the timer (TC1). TC1C must be reset whenever the TC1ENB is set to “1” to start
the timer. TC1C is incremented each time a clock pulse of the frequency determined by TC1RATE0 ~ TC1RATE2.
When TC1C has incremented to “0FFH”, it counts to “00H” an overflow generated. Under TC1 interrupt service request
(TC1IEN) enable condition, the TC1 interrupt request flag will be set to “1” and the system executes the interrupt
service routine. When TC1C overflows, the TC1C will be restored automatically if ALOAD1 of TC1M register is
enabled.
0DDH
Bit 7
Bit 6
Bit 5
Bit 4
TC1C
TC1C7
TC1C6
TC1C5
TC1C4
Read/Write
R/W
R/W
R/W
R/W
After reset
-
-
-
-
The basic timer table interval time of TC1.
High speed mode (fcpu = 3.58MHz / 4)
TC1RATE
TC1CLOCK
Max overflow interval
One step = max/256
000
fcpu/256
73.2 ms
286us
001
fcpu/128
36.6 ms
143us
010
fcpu/64
18.3 ms
71.5us
011
fcpu/32
9.15 ms
35.8us
100
fcpu/16
4.57 ms
17.9us
101
fcpu/8
2.28 ms
8.94us
110
fcpu/4
1.14 ms
4.47us
111
fcpu/2
0.57 ms
2.23us
The equation of TC1C initial value is as following.
TC1C initial value = 256 - (TC1 interrupt interval time * input clock)
Example: To set 10ms interval time for TC1 interrupt at 3.58MHz high-speed mode. TC1C value (74H) =
256 - (10ms * fcpu/64)
TC1C initial value = 256 - (TC1 interrupt interval time * input clock)
= 256 - (10ms * 3.58 * 10
6
/ 4 / 64)
= 256 - (10
-2
* 3.58 * 10
6
/ 4 / 64)
= 116
= 74H
Bit 3
TC1C3
R/W
-
Bit 2
TC1C2
R/W
-
Bit 1
TC1C1
R/W
-
Bit 0
TC1C0
R/W
-
Low speed mode (fcpu = 32768Hz / 4)
Max overflow interval
8000 ms
4000 ms
2000 ms
1000 ms
500 ms
250 ms
125 ms
62.5 ms
One step = max/256
31.25 ms
15.63 ms
7.8 ms
3.9 ms
1.95 ms
0.98 ms
0.49 ms
0.24 ms