参数资料
型号: SNJ54CDC341FKR
厂商: TEXAS INSTRUMENTS INC
元件分类: 时钟及定时
英文描述: CDC SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC20
封装: CERAMIC, LCC-20
文件页数: 1/10页
文件大小: 159K
代理商: SNJ54CDC341FKR
SN54CDC341
1-LINE TO 8-LINE CLOCK DRIVER
SGAS005A – MARCH 1996 – REVISED JULY 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
D Low Output Skew, Low Pulse Skew for
Clock-Distribution and Clock-Generation
Applications
D TTL-Compatible Inputs and Outputs
D Distributes One Clock Input to Eight
Outputs
D Distributed VCC and Ground Pins Reduce
Switching Noise
D High-Drive Outputs (–48-mA IOH,
48-mA IOL)
D State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
D Package Options Include Ceramic
Flatpacks (W), Ceramic Chip Carriers (FK),
and Ceramic (J) 300-mil DIPS
description
The SN54CDC341 is a high-performance clock-
driver circuit that distributes one (A) input signal to
eight (Y) outputs with minimum skew for clock
distribution. Through the use of the control pins
(1G and 2G), the outputs can be placed in a low
state regardless of the A input.
The propagation delays are adjusted at the factory
using the P0 and P1 pins. These pins are not
intended for customer use and should be strapped
to GND.
The SN54CDC341 is characterized for operation over the full military temperature range of –55
°C to 125°C.
FUNCTION TABLE
INPUTS
OUTPUTS
1G
2G
A
1Y1 – 1Y4
2Y1 – 2Y4
X
L
LH
L
HH
L
H
LH
H
L
H
Copyright
1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-
ΙΙB is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
1G
2G
A
P0
P1
VCC
2Y4
2Y3
GND
VCC
1Y1
1Y2
GND
1Y3
1Y4
GND
2Y1
2Y2
GND
J OR W PACKAGE
(TOP VIEW)
FK PACKAGE
(TOP VIEW)
32 1 20 19
9
4
5
6
7
8
18
17
16
15
14
A
P0
P1
VCC
2Y4
10 11 12 13
2Y3
GND
2Y2
2Y1
2G
1Y1
V
CC
V
CC
1G
1Y2
GND
1Y3
1Y4
GND
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