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参数资料
| 型号： | SNJ54HC165W |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 计数移位寄存器 |
| 英文描述： | HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, CDFP16 |
| 封装： | CERAMIC, DFP-16 |
| 文件页数： | 12/25页 |
| 文件大小： | 822K |
| 代理商： | SNJ54HC165W |
SN54HC165, SN74HC165
8BIT PARALLELLOAD SHIFT REGISTERS
SCLS116E DECEMBER 1982 REVISED SEPTEMBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK
INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high
transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK
is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the
register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.
FUNCTION TABLE
INPUTS
FUNCTION
SH/LD
CLK
CLK INH
FUNCTION
L
X
Parallel load
H
X
No change
H
X
H
No change
H
L
↑
Shift
H
↑
L
Shift
Shift = content of each internal register shifts
toward serial output QH. Data at SER is
shifted into the first register.
logic diagram (positive logic)
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
1
15
2
10
SH/LD
CLK INH
CLK
SER
9
7
QH
11
12
13
14
3
4
5
6
AB
C
D
EF
G
H
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SNJ54HC166FK | 制造商:Texas Instruments 功能描述: |
| SNJ54HC166J | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:5962-9050101QEA,PAR-LOAD 8-BIT SHIFT REG - Rail/Tube |
| SNJ54HC173FK | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SNJ54HC174J | 制造商:Texas Instruments 功能描述: |
| SNJ54HC175FK | 制造商:Texas Instruments 功能描述: |
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