参数资料
型号: SNJ54LV166AW
厂商: TEXAS INSTRUMENTS INC
元件分类: 计数移位寄存器
英文描述: LV/LV-A/LVX/H SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP16
封装: CERAMIC, DFP-16
文件页数: 16/19页
文件大小: 588K
代理商: SNJ54LV166AW
SN54LV166A, SN74LV166A
8BIT PARALLELLOAD SHIFT REGISTERS
SCLS456C FEBRUARY 2001 REVISED APRIL 2005
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
SN54LV166A
SN74LV166A
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
tw
Pulse duration
CLR low
8
9
ns
tw
Pulse duration
CLK high or low
8.5
9
ns
CLK INH before CLK
7
Data before CLK
6.5
8.5
tsu
Setup time
SH/LD before CLK
7
8.5
ns
tsu
Setup time
SER before CLK
8.5
9.5
ns
CLR
↑ inactive before CLK↑
6
7
th
Hold time
Data after CLK
0.5
0
ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
SN54LV166A
SN74LV166A
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
tw
Pulse duration
CLR low
6
7
ns
tw
Pulse duration
CLK high or low
6
7
ns
CLK INH before CLK
5
Data before CLK
5
6
tsu
Setup time
SH/LD before CLK
5
6
ns
tsu
Setup time
SER before CLK
5
6
ns
CLR
↑ inactive before CLK↑
4
th
Hold time
Data after CLK
0
ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
SN54LV166A
SN74LV166A
UNIT
MIN
MAX
MIN
MAX
MIN4
MAX
UNIT
tw
Pulse duration
CLR low
5
ns
tw
Pulse duration
CLK high or low
4
ns
CLK INH before CLK
3.5
Data before CLK
4.5
tsu
Setup time
SH/LD before CLK
4
ns
tsu
Setup time
SER before CLK
4
ns
CLR
↑ inactive before CLK↑
3.5
th
Hold time
Data after CLK
1
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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