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参数资料
| 型号： | SNJ54LVT162245AWD |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 总线收发器 |
| 英文描述： | LVT SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, CDFP48 |
| 封装： | CERAMIC, DFP-48 |
| 文件页数： | 1/17页 |
| 文件大小： | 529K |
| 代理商： | SNJ54LVT162245AWD |
www.ti.com
FEATURES
SN54LVT162245A . . . WD PACKAGE
SN74LVT162245A . . . DGG OR DL PACKAGE
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1DIR
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2DIR
1OE
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE
DESCRIPTION/ORDERING INFORMATION
3.3-V ABT 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS714D – FEBRUARY 2000 – REVISED NOVEMBER 2006
Members of the Texas Instruments Widebus
Family
A-Port Outputs Have Equivalent 22- Series
Resistors, So No External Resistors Are
Required
Supprt Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)
Support Unregulated Battery Operation Down
to 2.7 V
Typical V
OLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
I
off and Power-Up 3-State Support Hot
Insertion
Distributed V
CC and GND Pins Minimize
High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
–
2000-V Human-Body Model (A114-A)
–
200-V Machine Model (A115-A)
–
1000-V Charged-Device Model (C101)
The 'LVT162245A devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for low-voltage
(3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
These devices are designed for asynchronous communication between two data buses. The logic levels of the
direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port
outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to
the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are
activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level
applied to prevent excess ICC and ICCZ.
The A-port outputs, which are designed to source or sink up to 12 mA, include equivalent 22-
series resistors
to reduce overshoot and undershoot.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
UNLESS
OTHERWISE
NOTED
this
document
contains
Copyright 2000–2006, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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