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参数资料
| 型号： | SNJ54LVTH273FK |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 锁存器 |
| 英文描述： | LVT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC20 |
| 封装： | CERAMIC, LCC-20 |
| 文件页数： | 10/15页 |
| 文件大小： | 491K |
| 代理商： | SNJ54LVTH273FK |
SN54LVTH273, SN74LVTH273
3.3V ABT OCTAL DTYPE FLIPFLOPS
WITH CLEAR
SCBS136M MAY 1992 REVISED OCTOBER 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54LVTH273
SN74LVTH273
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = 2.7 V,
II = 18 mA
1.2
V
VCC = 2.7 V to 3.6 V,
IOH = 100 A
VCC0.2
VOH
VCC = 2.7 V,
IOH = 8 mA
2.4
V
VOH
VCC = 3 V
IOH = 24 mA
2
V
VCC = 3 V
IOH = 32 mA
2
VCC = 2.7 V
IOL = 100 A
0.2
VCC = 2.7 V
IOL = 24 mA
0.5
VOL
IOL = 16 mA
0.4
V
VOL
VCC = 3 V
IOL = 32 mA
0.5
V
VCC = 3 V
IOL = 48 mA
0.55
IOL = 64 mA
0.55
VCC = 0 or 3.6 V,
VI = 5.5 V
10
II
Control inputs
VCC = 3.6 V,
VI = VCC or GND
±1
A
II
Data inputs
VCC = 3.6 V
VI = VCC
1
A
Data inputs
VCC = 3.6 V
VI = 0
5
Ioff
VCC = 0,
VI or VO = 0 to 4.5 V
±100
A
VCC = 3 V
VI = 0.8 V
75
II(hold)
Data inputs
VCC = 3 V
VI = 2 V
75
A
II(hold)
Data inputs
VCC = 3.6 V,
VI = 0 to 3.6 V
500
750
A
ICC
VCC = 3.6 V, IO = 0,
Outputs high
0.19
mA
ICC
VCC = 3.6 V, IO = 0,
VI = VCC or GND
Outputs low
5
mA
ICC§
VCC = 3 V to 3.6 V, One input at VCC 0.6 V,
Other inputs at VCC or GND
0.2
mA
Ci
VI = 3 V or 0
4
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVTH273
SN74LVTH273
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
fclock
Clock frequency
150
MHz
tw
Pulse duration
3.3
ns
tsu
Setup time
Data high or low before CLK
↑
2.3
2.7
2.3
2.7
ns
tsu
Setup time
CLR high before CLK
↑
2.3
2.7
2.3
2.7
ns
th
Hold time, data high or low after CLK
↑
0
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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