- 您现在的位置：买卖IC网 > PDF目录98141 > SNJ54LVTH652FK (TEXAS INSTRUMENTS INC) LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CQCC28 PDF资料下载
参数资料
| 型号： | SNJ54LVTH652FK |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 总线收发器 |
| 英文描述： | LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CQCC28 |
| 封装： | CERAMIC, LCC-28 |
| 文件页数： | 11/18页 |
| 文件大小： | 549K |
| 代理商： | SNJ54LVTH652FK |
SN54LVTH652, SN74LVTH652
3.3V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3STATE OUTPUTS
SCBS706F AUGUST 1997 REVISED OCTOBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
The ’LVTH652 devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the data bus or from the internal storage registers.
Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB
and SBA) inputs are provided to select whether real-time or stored data is transferred. The circuitry used for
select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between
real-time and stored data. A low input selects real-time data and a high input selects stored data. Figure 1
illustrates the four fundamental bus-management functions that can be performed with the ’LVTH652 devices.
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at
the appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB
and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops
by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input; therefore,
when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains
at its last state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup
or pulldown resistors with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor
and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by
the current-sinking/current-sourcing capability of the driver.
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
FUNCTION TABLE
INPUTS
DATA I/O
OPERATION OR FUNCTION
OEAB
OEBA
CLKAB
CLKBA
SAB
SBA
A1A8
B1B8
OPERATION OR FUNCTION
L
H
H or L
X
Input
Isolation
L
H
↑↑
X
Input
Store A and B data
X
H
↑
H or L
X
Input
Unspecified
Store A, hold B
H
↑↑
X
Input
Output
Store A in both registers
L
X
H or L
↑
X
Unspecified
Input
Hold A, store B
L
↑↑
XX
Output
Input
Store B in both registers
L
X
L
Output
Input
Real-time B data to A bus
L
X
H or L
X
H
Output
Input
Stored B data to A bus
H
X
L
X
Input
Output
Real-time A data to B bus
H
H or L
X
H
X
Input
Output
Stored A data to B bus
H
L
H or L
H
Output
Stored A data to B bus and
stored B data to A bus
The data-output functions can be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions always are
enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.
相关PDF资料 |
PDF描述 |
|---|---|
| SNJ54LVU04AW | LVU SERIES, HEX 1-INPUT INVERT GATE, CDFP14 |
| SNJ54S140J | S SERIES, DUAL 4-INPUT NAND GATE, CDIP14 |
| SNV54HC08W | HC/UH SERIES, QUAD 2-INPUT AND GATE, CDFP14 |
| SN74HC08DT | HC/UH SERIES, QUAD 2-INPUT AND GATE, PDSO14 |
| SPAK56853FG120 | 16-BIT, 4 MHz, OTHER DSP, PQFP128 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SNJ54S00J | 制造商:Texas Instruments 功能描述:2-INPUT NAND GATE |
| SNJ54S00W | 制造商:Texas Instruments 功能描述:NAND Gate 4-Element 2-IN Bipolar 14-Pin CFPAK Tube |
| SNJ54S02J | 制造商:Texas Instruments 功能描述:NOR Gate 4-Element 2-IN Bipolar 14-Pin CDIP Tube 制造商:Rochester Electronics LLC 功能描述:2-INPUT NOR GATE - Bulk |
| SNJ54S04FK | 制造商:Texas Instruments 功能描述: |
| SNJ54S04J | 制造商:Texas Instruments 功能描述:Inverter 6-Element Bipolar 14-Pin CDIP Tube 制造商:Texas Instruments 功能描述:INVERTER 6-ELEM BIPOLAR 14CDIP - Rail/Tube |
发布紧急采购，3分钟左右您将得到回复。