参数资料
型号: SP6121EB
厂商: Exar Corporation
文件页数: 7/16页
文件大小: 0K
描述: EVAL BOARD FOR SP6121
标准包装: 1
系列: *
THEORY OF OPERATION
Over Current Protection
Over current protection on the SP6121 is imple-
mented through detection of an excess voltage
condition across the high side PMOS switch
during conduction. This is typically referred to
as high side R DS(ON) detection and eliminates the
need of an external sense resistor. The over
current comparator charges an internal sam-
pling capacitor each time V (ISET) - V (ISENSE)
exceeds the 160mV (typ) internal threshold and
the PDRV voltage is low. The discharge/charge
current ratio on the sampling capacitor is about
2%. Therefore, provided that the over current
condition persists, the capacitor voltage will be
pumped up during each time PDRV switches
low. This voltage will trigger an over current
condition upon reaching a CMOS inverter thresh-
old. There are many advantages to this ap-
proach. First, the filtering action of the gated S/
H scheme protects against false and undesirable
triggering that could occur during a minor tran-
Output Drivers
The SP6121, unlike some other bipolar control-
ler IC’s, incorporates gate drivers with rail-to-
rail swing that help prevent spurious turn on due
to capacitive coupling. The driver stage consists
of one high side PMOS, 4 ? driver, PDRV, and
one low side, 4 ? , NFET driver, NDRV, opti-
mized for driving external power MOSFET’s in
a synchronous buck topology. The output driv-
ers also provide gate drive non-overlap mecha-
nism that provides a dead time between PDRV
and NDRV transitions to avoid potential shoot-
through problems in the external MOSFET’s.
Figure 3 shows typical waveforms for the output
drivers. As with all synchronous designs, care
must be taken to ensure that the MOSFETs are
properly chosen for non-overlap time, enhance-
ment gate drive voltage, “on” resistance R DS(ON) ,
reverse transfer capacitance Crss, input voltage
and maximum output current.
Vcc-2 V
sient overload condition or supply line noise.
Furthermore, the total amount of time to trigger
the fault depends on the on-time of the PMOS
5V
GATE DRIVER TEST CONDITIONS
90 %
switch. Ten, 1 μ s pulses are equivalent to twenty,
PDRV(NDRV)
FALL TIME
NON-OVERLAP
500ns pulses or one, 10 μ s pulse, however, de-
pending on the period, each scenario takes a
different amount of total time to trigger a fault.
Therefore, the fault becomes an indicator of
5V
10 %
RISE TIME
90 %
average power in the PMOS switch.
Although the 160 mV internal threshold is fixed,
the overall R DS(ON) detection voltage can be
increased by placing a resistor from I SET to the
source of the PMOS. A 30 μ A sink current pro-
grams the additional voltage.
In order for the current limit circuit to operate
properly and accurately, the I SET and I SENSE pins
must be Kelvin connected to the high side
PMOS’s source and drain pins.
The 160mV threshold and 30 μ A I SET current
have 3300 ppm/ ° C temperature coefficients in
an effort to first order match the thermal charac-
teristics of the R DS(ON) of the PMOS switch. It
assumed that the SP6121 will be used in com-
pact designs where there is a high amount of
thermal coupling between the PMOS and the
controller.
NDRV(PDRV)
V(V CC )
PDRV
Voltage
0V
V(V CC )
NDRV
Voltage
0V
V(V CC =V IN )
SWN
Voltage
~0V
- V(Diode) V
TIME
2V
10 %
Figure 3. SP6121 Output Driver Waveforms.
Date: 11/29/04
SP6121 Low Voltage, Synchronous Step Down PWM Controller
7
? Copyright 2004 Sipex Corporation
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