参数资料
型号: SP6128ASEY-L
厂商: Exar Corporation
文件页数: 7/10页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 14TSSOP
标准包装: 94
PWM 型: 电压模式
输出数: 1
频率 - 最大: 330kHz
占空比: 90%
电源电压: 3 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 14-TSSOP(0.173",4.40mm 宽)
包装: 管件
OPERATION: continued
A more detailed description of the waveform is shown below.
SP6128A OVER CURRENT (HICCUP MODE)
Test Conditions
V FB = 0.7V
V CC = PV CC = 5.0V
BST = 5.0V
SWN - tied to GND through 1k Resistor
COMP – released from GND
Overcurrent Detected
G H Turns Off
Fault Mode Enabled
Internal SSTART rises until
~ V CC -1V, then gives command
to attempt RESTART
G H
COMP Clamps
~ 3V
COMP
After pop, COMP
ENABLE
Part
retains internal
SSTART slope
Attempt
RESTART
5 μ A PULLUP slope to 0.3V;
35 μ A PULLUP to 0.7V
Internal SSTART
passes V(V FB ), COMP
pops to ~ internal
SSTART voltage +0.7V
Over Current Protection
Over current protection on the SP6128A is imple-
mented through detection of an excess voltage
condition across the high side NMOS switch
during conduction. This is typically referred to
as high side R DS(ON) detection and eliminates the
need of an external sense resistor. The over
current comparator charges an internal sam-
pling capacitor each time V SWN is lower than
(V ISET - 140mV) and the GH voltage is high. The
discharge/charge current ratio on the sampling
capacitor is about 2%. Therefore, provided that
the over current condition persists, the capacitor
voltage will be pumped up during each time GH
switches high. This voltage will trigger an over
current condition upon reaching a CMOS in-
verter threshold. There are many advantages to
this approach. First, the filtering action of the
gated scheme protects against false and undesir-
able triggering that could occur during a minor
transient overload condition or supply line noise.
Furthermore, the total amount of time to trigger
the fault depends on the on-time of the high side
NMOS switch. Fifteen, 1 μ s pulses are equiva-
lent to thirty, 500ns pulses or one, 15 μ s pulse,
however, depending on the period, each sce-
nario takes a different amount of total time to
trigger a fault. Therefore, the fault becomes an
indicator of average power in the high side
Rev. 08/19/05
SP6128A Low Voltage, Synchronous Step Down PWM Controller
7
? Copyright 2005 Sipex Corporation
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