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参数资料
| 型号： | SP6652EU-L/TR |
| 厂商： | Exar Corporation |
| 文件页数： | 6/16页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 1A 10MSOP |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.9 V ~ 5 V |
| 输入电压： | 2.85 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1.4MHz |
| 电流 - 输出： | 1A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 10-MSOP |
DETAILED DESCRIPTION
when the output voltage is low. The inductor
current tends to rise until the energy loss
from the discharge resistances are equal to
the energy gained during the charge phase.
For this reason, the clock frequency is cut in
half when the feedback pin is below 0.3V, ef -
fectively reducing the minimum duty cycle in
half. Above V( FB ) = 0.3V the clock frequency
is normal (see Typical Operating Character -
istics: Inductor Current vs. V OUT )
Voltage Loop and Compensation
in PWM Mode
The voltage loop section of the circuit con -
sists of the error amplifier and the translator
circuits (see functional diagram). The input
of the voltage loop is the 0.8V reference volt -
age minus the divided down output voltage
at the feedback pin. The output of the error
amplifier is translated from a ground referred
signal (the COMP node) to a power input
voltage referred signal. The output of the
voltage loop is fed to the positive terminal
of the Current Loop comparator, and repre -
sents the peak inductor current necessary
to close the loop.
1 20K 2 2.0M 3 50K
The total power supply loop is compensated
with a series RC network connected from
the COMP pin to ground. Compensation is
simple due to current-mode control. The
modulator has two dominant poles: one at a
low frequency, and one above the crossover
frequency of the loop, as seen in the graph
below, Linearized Modulator Frequency
Response vs. Inductor Value.
The low frequency pole for L1= 5μH is
4kHz, the second pole is 500kHz, and the
gain-bandwidth is 20kHz. The total loop
crossover frequency is chosen to be 200kHz,
which is 1/6 th of the clock frequency. This
sets the second modulator pole at 2.5 times
the crossover frequency. Therefore the gain
of the error amplifier can be 200kHz/20kHz
= 10 at the first modulator pole of 4kHz. The
error amp transconductance is 1mA/V, so
this sets the R Z resistor value in the com -
pensation network at 10/1mA/V = 10k?.
The zero frequency is placed at the first
pole to provide at total system response of
-20dB/decade (the zero from the error amp
cancels the first modulator pole, leaving the
16K
12K
8K
4K
1.6M
1.2M
0.8M
0.4M
40K
30K
20K
10K
0
0
>>
0
2u 3u 4u 5u 6u
1 Mod_pole1 2 Mod_pole2 3 Gbw_modfb
7u
8u
9u
10u
L1VAL
Conditions: V IN =5V, V OUT =3.3V, f CLK =1.4MHz, C OUT =10μF, and MC V =132mV/μs. The inductor is varied from
2μH to 10μH
Linearized Modulator Frequency Response vs. Inductor
Oct10-07 RevJ
SP6652 1A, High Efficiency, Current Mode PWM Buck Regulator
6
? 2007 Sipex Corporation
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